GS88118/32/36C(T/D)-xxxI
333 MHz150 MHz
512K x 18, 256K x 32, 256K x 36
100-pin TQFP & 165-bump BGA
2.5 V or 3.3 V V
DD
Industrial Temp
9Mb Sync Burst SRAMs
2.5 V or 3.3 V I/O
Flow Through/Pipeline Reads
Features
The function of the Data Output register can be controlled by
IEEE 1149.1 JTAG-compatible Boundary Scan
the user via the FT mode pin (Pin 14). Holding the FT mode
2.5 V or 3.3 V +10%/10% core power supply
pin low places the RAM in Flow Through mode, causing
2.5 V or 3.3 V I/O supply
output data to bypass the Data Output Register. Holding FT
LBO pin for Linear or Interleaved Burst mode
high places the RAM in Pipeline mode, activating the rising-
Internal input resistors on mode pins allow floating mode pins
edge-triggered Data Output Register.
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
SCD Pipelined Reads
Automatic power-down for portable applications
The GS88118C(T/D)/GS88132C(88132CT/D)/GS88136C(T/
JEDEC-standard 100-lead TQFP and 165-bump BGA
D) is a SCD (Single Cycle Deselect) pipelined synchronous
packages
SRAM. DCD (Dual Cycle Deselect) versions are also
RoHS-compliant 100-lead TQFP and 165-bump BGA
available. SCD SRAMs pipeline deselect commands one stage
packages available
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
Functional Description captured in the input registers.
Applications Byte Write and Global Write
The GS88118C(T/D)/GS88132C(T/D)/GS88136C(T/D) is a Byte write operation is performed by using Byte Write enable
9,437,184-bit high performance synchronous SRAM with a 2- (BW) input combined with one or more individual byte write
bit burst address counter. Although of a type originally signals (Bx). In addition, Global Write (GW) is available for
developed for Level 2 Cache applications supporting high writing all bytes at one time, regardless of the Byte Write
performance CPUs, the device now finds application in control inputs.
synchronous SRAM applications, ranging from DSP main
Sleep Mode
store to networking chip set support.
Low power (Sleep mode) is attained through the assertion
Controls (High) of the ZZ signal, or by stopping the clock (CK).
Addresses, data I/Os, chip enable (E1, E2), address burst Memory data is retained during Sleep mode.
control inputs (ADSP, ADSC, ADV) and write control inputs
Core and Interface Voltages
(Bx, BW, GW) are synchronous and are controlled by a
The GS88118C(T/D)/GS88132C(T/D)/GS88136C(T/D)
positive-edge-triggered clock input (CK). Output enable (G)
operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V
and power down control (ZZ) are asynchronous inputs. Burst
and 2.5 V compatible. Separate output power (V ) pins are
DDQ
cycles can be initiated with either ADSP or ADSC inputs. In
used to decouple output noise from the internal circuits and are
Burst mode, subsequent burst addresses are generated
3.3 V and 2.5 V compatible.
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Parameter Synopsis
-333I -300I -250I -200I -150I Unit
t 2.5 2.5 2.5 3.0 3.8 ns
KQ
3.0 3.3 4.0 5.0 6.7 ns
Pipeline tCycle
3-1-1-1
Curr (x18) 260 245 215 190 160 mA
Curr (x32/x36) 300 280 245 215 180 mA
t
4.5 5.0 5.5 6.5 7.5 ns
KQ
4.5 5.0 5.5 6.5 7.5 ns
Flow Through tCycle
2-1-1-1
Curr (x18) 200 185 180 160 148 mA
Curr (x32/x36) 225 210 200 180 165 mA
Rev: 1.04a 10/2012 1/35 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see GS88118/32/36C(T/D)-xxxI
GS88118C 100-Pin TQFP Pinout (Package T)
10099 989796959493929190898887868584838281
A
NC
1 80
NC
NC 2 79
NC
NC 3 78
V
V
DDQ 4 77
DDQ
V
V 5
76 SS
SS
NC
NC 6
75
DQPA
7
NC 74
DQA
DQB 8 73
DQA
DQB 9 72
512K x 18
V
V 10 71
SS
SS
V
V 11 Top View 70
DDQ
DDQ
DQA
DQB 12 69
DQA
13
DQB 68
V
14
FT 67
SS
NC
V 15 66
DD
V
NC 16 65
DD
ZZ
V 17 64
SS
DQA
DQB 18 63
DQA
19 62
DQB
V V
20 61
DDQ
DDQ
V
V 21 60
SS SS
DQA
22
DQB 59
23 DQA
DQB 58
NC
DQPB 24 57
NC
25 56
NC
V
26 55
V
SS
SS
V
27 54
V
DDQ
DDQ
NC
28 53
NC
29 52 NC
NC
30 NC
NC 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note:
Pins marked with NC can be tied to either V or V . These pins can also be left floating.
DD SS
Rev: 1.04a 10/2012 2/35 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see