GS881Z18/32/36C(T/D)-xxxI 333 MHz150 MHz 9Mb Pipelined and Flow Through 100-Pin TQFP & 165-Bump BGA 2.5 V or 3.3 V V DD Industrial Temp Synchronous NBT SRAM 2.5 V or 3.3 V I/O Because it is a synchronous device, address, data inputs, and Features read/ write control inputs are captured on the rising edge of the User-configurable Pipeline and Flow Through mode input clock. Burst order control (LBO) must be tied to a power NBT (No Bus Turn Around) functionality allows zero wait rail for proper operation. Asynchronous inputs include the read-write-read bus utilization Sleep mode enable, ZZ and Output Enable. Output Enable can Fully pin-compatible with both pipelined and flow through be used to override the synchronous control of the output NtRAM, NoBL and ZBT SRAMs drivers and turn the RAM s output drivers off at any time. IEEE 1149.1 JTAG-compatible Boundary Scan Write cycles are internally self-timed and initiated by the rising 2.5 V or 3.3 V +10%/10% core power supply edge of the clock input. This feature eliminates complex off- 2.5 V or 3.3 V I/O supply chip write pulse generation required by asynchronous SRAMs LBO pin for Linear or Interleave Burst mode and simplifies input signal timing. Pin-compatible with 2M, 4M, and 18M devices Byte write operation (9-bit Bytes) The GS881Z18C(T/D)/GS881Z32C(T/D)/GS881Z36C(T/D) 3 chip enable signals for easy depth expansion may be configured by the user to operate in Pipeline or Flow ZZ pin for automatic power-down Through mode. Operating as a pipelined synchronous device, JEDEC-standard packages in addition to the rising-edge-triggered registers that capture RoHS-compliant 100-lead TQFP and 165-bump BGA input signals, the device incorporates a rising-edge-triggered packages available output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during Functional Description the access cycle and then released to the output drivers at the The GS881Z18C(T/D)/GS881Z32C(T/D)/GS881Z36C(T/D) next rising edge of clock. is a 9Mbit Synchronous Static SRAM. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late The GS881Z18C(T/D)/GS881Z32C(T/D)/GS881Z36C(T/D) write or flow through read/single late write SRAMs, allow is implemented with GSI s high performance CMOS utilization of all available bus bandwidth by eliminating the technology and is available in a JEDEC-standard 100-pin need to insert deselect cycles when the device is switched from TQFP package. read to write cycles. Parameter Synopsis -333I -300I -250I -200I -150I Unit t 2.5 2.5 2.5 3.0 3.8 ns KQ 3.0 3.3 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 260 245 215 190 160 mA Curr (x32/x36) 300 280 245 215 180 mA t 4.5 5.0 5.5 6.5 7.5 ns KQ tCycle 4.5 5.0 5.5 6.5 7.5 ns Flow Through 2-1-1-1 Curr (x18) 200 185 180 160 148 mA Curr (x32/x36) 225 210 200 180 165 mA Rev: 1.04 7/2012 1/38 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS881Z18/32/36C(T/D)-xxxI GS881Z18CT 100-Pin TQFP Pinout (Package T) 10099 989796959493929190898887868584838281 A NC 1 80 NC NC 2 79 NC NC 3 78 V V DDQ 4 77 DDQ V V 5 76 SS SS NC NC 6 75 DQPA 7 NC 74 DQA DQB 8 73 DQA DQB 9 72 512K x 18 V V 10 71 SS SS V V 11 Top View 70 DDQ DDQ DQA DQB 12 69 DQA 13 DQB 68 V 14 FT 67 SS NC V 15 66 DD V NC 16 65 DD ZZ V 17 64 SS DQA DQB 18 63 DQA 19 62 DQB6 V V 20 61 DD DDQ V V 21 60 SS SS DQA 22 DQB 59 23 DQA DQB 58 NC DQPB 24 57 NC 25 56 NC V 26 55 V SS SS V 27 54 V DDQ DDQ NC 28 53 NC 29 52 NC NC 30 NC NC 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note: Pins marked with NC can be tied to either V or V . These pins can also be left floating. DD SS Rev: 1.04 7/2012 2/38 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see