GS88237CB-xxxI 333 MHz200 MHz 256K x 36 119-Bump BGA 2.5 V or 3.3 V V DD Industrial Temp 9Mb SCD/DCD Sync Burst SRAM 2.5 V or 3.3 V I/O SCD and DCD Pipelined Reads Features The GS88237CB is a SCD (Single Cycle Deselect) and DCD Single/Dual Cycle Deselect selectable (Dual Cycle Deselect) pipelined synchronous SRAM. DCD IEEE 1149.1 JTAG-compatible Boundary Scan SRAMs pipeline disable commands to the same degree as read ZQ mode pin for user-selectable high/low output drive commands. SCD SRAMs pipeline deselect commands one 2.5 V or 3.3 V +10%/10% core power supply stage less than read commands. SCD RAMs begin turning off 2.5 V or 3.3 V I/O supply their outputs immediately after the deselect command has been LBO pin for Linear or Interleaved Burst mode captured in the input registers. DCD RAMs hold the deselect Internal input resistors on mode pins allow floating mode pins command for one full cycle and then begin turning off their Default to SCD x18/x36 Interleaved Pipeline mode outputs just after the second rising edge of clock. The user may Byte Write (BW) and/or Global Write (GW) operation configure this SRAM for either mode of operation using the Internal self-timed write cycle SCD mode input. Automatic power-down for portable applications JEDEC-standard 119-bump BGA packages Byte Write and Global Write Ro-HS Compliant 119-bump BGA packages available Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for Functional Description writing all bytes at one time, regardless of the Byte Write Applications control inputs. The GS88237CB is a 9,437,184-bit high performance FLXDrive synchronous SRAM with a 2-bit burst address counter. The ZQ pin allows selection between high drive strength (ZQ Although of a type originally developed for Level 2 Cache low) for multi-drop bus applications and normal drive strength applications supporting high performance CPUs, the device (ZQ floating or high) point-to-point applications. See the now finds application in synchronous SRAM applications, Output Driver Characteristics chart for details. ranging from DSP main store to networking chip set support. Sleep Mode Controls Low power (Sleep mode) is attained through the assertion Addresses, data I/Os, chip enable (E1), address burst control (High) of the ZZ signal, or by stopping the clock (CK). inputs (ADSP, ADSC, ADV), and write control inputs (Bx, Memory data is retained during Sleep mode. BW, GW) are synchronous and are controlled by a positive- edge-triggered clock input (CK). Output enable (G) and power Core and Interface Voltages down control (ZZ) are asynchronous inputs. Burst cycles can The GS88237CB operates on a 2.5 V or 3.3 V power supply. be initiated with either ADSP or ADSC inputs. In Burst mode, All input are 3.3 V and 2.5 V compatible. Separate output subsequent burst addresses are generated internally and are power (V ) pins are used to decouple output noise from the DDQ controlled by ADV. The burst address counter may be internal circuits and are 3.3 V and 2.5 V compatible. configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Parameter Synopsis -333I -300I -250I -200I Unit Pipeline t 2.0 2.2 2.3 2.7 ns KQ 3-1-1-1 3.0 3.3 4.0 5.0 ns tCycle Curr (x36) 300 280 245 215 mA Rev: 1.05a 11/2012 1/25 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS88237CB-xxxI GS88237C Pad Out119-Bump BGATop View (Package B) 1234567 A V A A ADSP AA V DDQ DDQ B NC E2 A4 ADSC AA NC C NC A A V AA NC DD D DQC4 DQC9 V ZQ V DQB9 DQB4 SS SS DQC3 DQC8 V E1 V DQB8 DQB3 E SS SS F V DQC7 V G V DQB7 V DDQ SS SS DDQ G DQC2 DQC6 BC ADV BB DQB6 DQB2 H DQC1 DQC5 V GW V DQB5 DQB1 SS SS J V V NC V NC V V DDQ DD DD DD DDQ DQD1 DQD5 V CK V DQA5 DQA1 K SS SS L DQD2 DQD6 BD SCD BA DQA6 DQA2 M V DQD7 V BW V DQA7 V DDQ SS SS DDQ N DQD3 DQD8 V A1 V DQA8 DQA3 SS SS P DQD4 DQD9 V A0 V DQA9 DQA4 SS SS V / DDQ NC A LBO V APE R DD DNU T NC NC A10 A11 A12 NC ZZ U V TMS TDI TCK TDO NC V DDQ DDQ Rev: 1.05a 11/2012 2/25 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see