GS882Z18/36CB/D-xxx 333 MHz150 MHz 9Mb Pipelined and Flow Through 119-bump and 165-bump BGA 2.5 V or 3.3 V V DD Commercial Temp Synchronous NBT SRAM 2.5 V or 3.3 V I/O Features Functional Description NBT (No Bus Turn Around) functionality allows zero wait The GS882Z18/36C882Z18C is a 9Mbit Synchronous Static Read-Write-Read bus utilization fully pin-compatible with SRAM. GSI s NBT SRAMs, like ZBT, NtRAM, NoBL or both pipelined and flow through NtRAM, NoBL and other pipelined read/double late write or flow through read/ ZBT SRAMs single late write SRAMs, allow utilization of all available bus 2.5 V or 3.3 V +10%/10% core power supply bandwidth by eliminating the need to insert deselect cycles 2.5 V or 3.3 V I/O supply when the device is switched from read to write cycles. User-configurable Pipeline and Flow Through mode Because it is a synchronous device, address, data inputs, and ZQ mode pin for user-selectable high/low output drive read/write control inputs are captured on the rising edge of the IEEE 1149.1 JTAG-compatible Boundary Scan input clock. Burst order control (LBO) must be tied to a power LBO pin for Linear or Interleave Burst mode rail for proper operation. Asynchronous inputs include the Pin-compatible with 2M, 4M, and 18M devices Sleep mode enable (ZZ) and Output Enable. Output Enable can Byte write operation (9-bit Bytes) be used to override the synchronous control of the output 3 chip enable signals for easy depth expansion drivers and turn the RAM s output drivers off at any time. ZZ Pin for automatic power-down Write cycles are internally self-timed and initiated by the rising JEDEC-standard 119-bump BGA and 165-bump FPBGA edge of the clock input. This feature eliminates complex off- packages chip write pulse generation required by asynchronous SRAMs RoHS-compliant 119-bump and 165-bump BGA packages and simplifies input signal timing. available The GS882Z18/36C may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. The GS882Z18/36C is implemented with GSI s high performance CMOS technology and is available in JEDEC- standard 119-bump BGA and 165-bump FPBGA packages. Parameter Synopsis -333 -300 -250 -200 -150 Unit t 2.5 2.5 2.5 3.0 3.8 ns KQ 3.0 3.3 4.0 5.0 6.7 ns Pipeline tCycle 3-1-1-1 Curr (x18) 240 225 195 170 140 mA Curr (x32/x36) 280 260 225 195 160 mA t 4.5 5.0 5.5 6.5 7.5 ns KQ tCycle 4.5 5.0 5.5 6.5 7.5 ns Flow Through 2-1-1-1 Curr (x18) 180 165 160 140 128 mA Curr (x32/x36) 205 190 180 160 145 mA Rev: 1.05 7/2012 1/34 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see GS882Z18/36CB/D-xxx GS882Z36C Pad Out119-Bump BGATop View (Package B) 1234567 A V AA NC AA V DDQ DDQ B NC E2 AADVA E3 NC C NC A A V AA NC DD D DQC DQPC V ZQ V DQPB DQB SS SS E DQC DQC V E1 V DQB DQB SS SS F V DQC V G V DQB V DDQ SS SS DDQ G DQC DQC BC ABB DQB DQB H DQC DQC V W V DQB DQB SS SS J V V NC V NC V V DDQ DD DD DD DDQ K DQD DQD V CK V DQA DQA SS SS L DQD DQD BD NC BA DQA DQA M V DQD V CKE V DQA V DDQ SS SS DDQ N DQD DQD V A1 V DQA DQA SS SS P DQD DQPD V A0 V DQPA DQA SS SS R NC A LBO V FT APE DD T NC NC A A A NC ZZ U V TMS TDI TCK TDO NC V DDQ DDQ Rev: 1.05 7/2012 2/34 2011, GSI Technology Specifications cited are subject to change without notice. For latest documentation see