USE ULTRA37000 FOR CY7C341B ALL NEW DESIGNS 192-Macrocell MAX EPLD macrocells within each LAB. Each LAB is interconnected with Features a programmable interconnect array, allowing all signals to be 192 macrocells in 12 logic array blocks (LABs) routed throughout the chip. Eight dedicated inputs, 64 bidirectional I/O pins The speed and density of the CY7C341B allows it to be used Advanced 0.65-micron CMOS technology to increase in a wide range of applications, from replacement of large performance amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 37 times the functionality Programmable interconnect array of 20-pin PLDs, the CY7C341B allows the replacement of over 384 expander product terms 75 TTL devices. By replacing large amounts of logic, the CY7C341B reduces board space, part count, and increases Available in 84-pin HLCC, PLCC, and PGA packages system reliability. Functional Description Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8 macrocells are connected to I/O pins and eight are buried, The CY7C341B is an Erasable Programmable Logic Device while for LABs B, C, D, E, H, I, J, and K, four macrocells are (EPLD) in which CMOS EPROM cells are used to configure connected to I/O pins and 12 are buried. Moreover, in addition logic functions within the device. The MAX architecture is to the I/O and buried macrocells, there are 32 single product 100% user-configurable, allowing the devices to accom- term logic expanders in each LAB. Their use greatly enhances modate a variety of independent logic functions. the capability of the macrocells without increasing the number The 192 macrocells in the CY7C341B are divided into 12 Logic of product terms in each macrocell. Array Blocks (LABs), 16 per LAB. There are 384 expander product terms, 32 per LAB, to be used and shared by the Selection Guide 7C341B-25 7C341B-35 Unit Maximum Access Time 25 35 ns Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600 Document : 38-03016 Rev. *C Revised April 22, 2004 + Feedback USE ULTRA37000 FOR ALL NEW DESIGNS CY7C341B 1 (A6) INPUT/CLK INPUT (C6) 84 2 (A5) INPUT INPUT (C7) 83 Logic Block Diagram 41 (K6) INPUT INPUT (L7) 44 42 (J6) INPUT INPUT (J7) 43 SYSTEMCLOCK LAB A LAB G 4(C5) MACROCELL1 MACROCELL97 46 (L6) 5(A4) MACROCELL2 MACROCELL98 47 (L8) 6(B4) MACROCELL3 MACROCELL99 48 (K8) 7(A3) MACROCELL4 MACROCELL100 49 (L9) 8(A2) MACROCELL5 MACROCELL101 50 (L10) 9(B3) MACROCELL6 MACROCELL102 51 (K9) 10 (A1) MACROCELL7 MACROCELL103 52 (L11) 11 (B2) MACROCELL8 MACROCELL104 53 (K10) MACROCELL 916 MACROCELL 105112 LAB B LAB H 12 (C2) MACROCELL17 MACROCELL113 54 (J10) 13 (B1) MACROCELL18 MACROCELL114 55 (K11) 14 (C1) MACROCELL19 MACROCELL115 56 (J11) 15 (D2) MACROCELL20 MACROCELL116 57 (H10) MACROCELL 2132 MACROCELL 117128 LAB C LAB I 16 (D1) MACROCELL33 MACROCELL129 58 (H11) P 17 (E3) MACROCELL34 MACROCELL130 59 (F10) 20 (F2) MACROCELL35 MACROCELL131 62 (G9) I 21 (F3) MACROCELL36 MACROCELL132 63 (F9) A MACROCELL 3748 MACROCELL 133144 LAB D LAB J 22 (G3) MACROCELL49 MACROCELL145 64 (F11) 23 (G1) MACROCELL50 MACROCELL146 65 (E11) 25 (F1) MACROCELL51 MACROCELL147 67 (E9) 26 (H1) MACROCELL52 MACROCELL148 68 (D11) MACROCELL 5364 MACROCELL 149160 LAB E LAB K 27 (H2) MACROCELL65 MACROCELL161 69 (D10) 28 (J1) MACROCELL66 MACROCELL162 70 (C11) 29 (K1) MACROCELL67 MACROCELL163 71 (B11) 30 (J2) MACROCELL68 MACROCELL164 72 (C10) MACROCELL 6980 MACROCELL 165176 LAB F LAB L 31 (L1) MACROCELL81 MACROCELL177 73 (A11) 32 (K2) MACROCELL82 MACROCELL178 74 (B10) 33 (K3) MACROCELL83 MACROCELL179 75 (B9) 34 (L2) MACROCELL84 MACROCELL180 76 (A10) MACROCELL85 MACROCELL181 35 (L3) 77 (A9) 36 (K4) MACROCELL86 MACROCELL182 78 (B8) MACROCELL87 MACROCELL183 37 (L4) 79 (A8) 38 (J5) MACROCELL88 MACROCELL184 80 (B6) MACROCELL 8996 MACROCELL 185192 () PERTAIN TO 84-PIN PGA PACKAGE 3, 24, 45, 66 (B5, G2, K7, E10) V CC 18, 19, 39, 40, 60, 61, 81, 82 (E1, E2, K5, L5, G10, G11, A7, B7) GND Document : 38-03016 Rev. *C Page 2 of 12 + Feedback