CY7C375i UltraLogic 128-Macrocell Flash CPLD 3.3V or 5.0V I/O operation Features Available in 160-pin TQFP, CQFP, and PGA packages 128 macrocells in eight logic blocks Functional Description 128 I/O pins Five dedicated inputs including 4 clock pins The CY7C375i is an In-System Reprogrammable Complex In-System Reprogrammable (ISR) Flash technology Programmable Logic Device (CPLD) and is part of the FLASH370i family of high-density, high-speed CPLDs. Like JTAG Interface all members of the FLASH370i family, the CY7C375i is Bus Hold capabilities on all I/Os and dedicated inputs designed to bring the ease of use and high performance of the 22V10 to high-density PLDs. No hidden delays Like all of the UltraLogic FLASH370i devices, the CY7C375i High speed is electrically erasable and In-System Reprogrammable (ISR), f = 125 MHz MAX which simplifies both design and manufacturing flows thereby t = 10 ns reducing costs. The Cypress ISR function is implemented PD through a JTAG serial interface. Data is shifted in and out t = 5.5 ns S through the SDI and SDO pins. The ISR interface is enabled t = 6.5 ns CO using the programming voltage pin (ISR ). Additionally, EN because of the superior routability of the FLASH370i devices, Fully PCI compliant ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments. Clock Inputs Inputs Logic Block Diagram 1 4 INPUT/CLOCK INPUT MACROCELL MACROCELLS 4 4 16 I/Os LOGIC LOGIC 16 I/Os I/O I/O BLOCK 0 15 36 36 BLOCK I/O I/O 112 127 A H PIM 16 16 16 I/Os LOGIC LOGIC 16 I/Os BLOCK 36 36 BLOCK I/O I/O I/O I/O 16 31 96 111 B G 16 16 16 I/Os LOGIC LOGIC 16 I/Os BLOCK 36 36 BLOCK I/O I/O I/O I/O 32 47 80 95 C F 16 16 16 I/Os 16 I/Os LOGIC LOGIC BLOCK 36 36 BLOCK I/O I/O I/O I/O 48 63 64 79 D E 16 16 64 64 Selection Guide 7C375i125 7C375i100 7C375i83 7C375iL83 7C375i66 7C375iL66 Unit 1 Maximum Propagation Delay , t 10 12 15 15 20 20 ns PD Minimum Set-Up, t 5.5 6 8 8 10 10 ns S 1 Maximum Clock to Output , t 6.5 7 8 8 10 10 ns CO Typical Supply Current, I 125 125 125 75 125 75 mA CC Note: 1. The 3.3V I/O mode timing adder, t , must be added to this specification when V = 3.3V 3.3IO CCIO Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600 Document : 38-03029 Rev. *A Revised May 10, 2004 CY7C375i Pin Configurations Top View TQFP GND 120 V 1 CCIO I/O 119 I/O 16 111 2 I/O 17 118 I/O 3 110 I/O 18 117 I/O 4 109 I/O 19 116 I/O /SDI 5 108 I/O /SCLK I/O 20 115 107 6 I/O 114 I/O 21 106 7 I/O 113 I/O 22 8 105 I/O 23 112 I/O 104 9 GND 111 GND 10 I/O 110 I/O 24 11 103 I/O 109 I/O 25 102 12 I/O 108 I/O 26 101 13 I/O I/O 27 107 14 100 I/O 28 106 I/O 99 15 I/O 29 105 16 I/O 98 I/O 104 I/O 17 30 97 I/O 103 I/O 31 96 18 CLK /I 102 CLK /I 0 0 3 4 19 V CCIO 101 GND 20 GND 100 V CCIO 21 CLK /I 1 1 99 CLK /I 22 2 3 I/O I/O 98 95 32 23 I/O 97 I/O 33 94 24 I/O 96 I/O 34 25 93 I/O 35 95 I/O 26 92 I/O 36 94 I/O 27 91 I/O I/O 37 28 93 90 I/O 92 38 I/O 29 89 I/O 91 I/O 39 88 30 GND GND 90 31 I/O 40 89 I/O 32 87 I/O 41 88 I/O 86 33 I/O 87 I/O 42 34 85 I/O 86 43 I/O 35 84 I/O 85 44 I/O 36 83 I/O 84 I/O 45 37 82 I/O 46 83 38 I/O 81 I/O 47 39 82 I/O 80 V CCIO GND 40 81 Document : 38-03029 Rev. *A Page 2 of 17 GND 41 160 V CCIO I/O 42 159 48 I/O 15 I/O 158 43 49 I/O 14 I/O 157 44 50 I/O 13 I/O 156 45 51 I/O 12 46 155 I/O /SMODE I/O 52 11 I/O 47 154 I/O 53 10 I/O I/O 48 153 9 54 I/O I/O 152 49 8 55 GND 151 50 GND I/O 150 56 51 I/O 7 I/O 57 52 149 I/O 6 I/O 58 53 148 I/O 5 I/O 147 59 54 I/O 4 I/O 146 60 55 I/O 3 I/O 145 61 56 I/O 2 I/O 57 144 62 I/O 1 I/O 58 143 I/O 63 0 I V 2 59 142 CCIO V 141 60 GND CCIO GND 61 140 V CCINT V 139 62 ISR CCINT EN 63 138 I/O I/O 64 127 I/O 64 137 I/O 65 126 I/O 65 136 I/O 66 125 I/O 66 135 I/O 67 124 I/O 67 134 I/O 68 123 I/O I/O 68 133 122 69 69 132 I/O I/O 121 70 I/O 70 131 I/O 71 120 71 GND GND 130 I/O 72 72 129 I/O 119 I/O 73 128 73 I/O 118 I/O 74 74 127 I/O 117 I/O 75 75 126 I/O 116 I/O /SDO 76 76 125 I/O 115 I/O 77 77 124 I/O 114 I/O 78 123 I/O 78 113 I/O I/O 79 122 79 112 V 80 121 GND CCIO