Ultra37000 CPLD Family 5V, 3.3V, ISR High-Performance CPLDs Features General Description In-System Reprogrammable (ISR) CMOS CPLDs The Ultra37000 family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled JTAG interface for reconfigurability system performance. The Ultra37000 family is designed to Design changes do not cause pinout changes bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number Design changes do not cause timing changes of logic blocks that are connected by a Programmable Inter- High density connect Matrix (PIM). Each logic block features its own 32 to 512 macrocells product term array, product term allocator, and 16 macrocells. The PIM distributes signals from the logic block outputs and all 32 to 264 I/O pins input pins to the logic block inputs. Five dedicated inputs including four clock pins All of the Ultra37000 devices are electrically erasable and Simple timing model In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The No fanout delays ISR feature provides the ability to reconfigure the devices No expander delays without having design changes cause pinout or timing No dedicated vs. I/O pin delays changes. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out No additional delay through PIM through the TDI and TDO pins, respectively. Because of the No penalty for using full 16 product terms superior routability and simple timing model of the Ultra37000 devices, ISR allows users to change existing logic designs No delay for steering or sharing product terms while simultaneously fixing pinout assignments and 3.3V and 5V versions maintaining system performance. 1 PCI-compatible The entire family features JTAG for ISR and boundary scan, Programmable bus-hold capabilities on all I/Os and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Intelligent product term allocator provides: Ultra37000 family features user programmable bus-hold 0 to 16 product terms to any macrocell capabilities on all I/Os. Product term steering on an individual basis Ultra37000 5.0V Devices Product term sharing among local macrocells The Ultra37000 devices operate with a 5V supply and can Flexible clocking support 5V or 3.3V I/O levels. V connections provide the CCO capability of interfacing to either a 5V or 3.3V bus. By Four synchronous clocks per device connecting the V pins to 5V the user insures 5V TTL levels CCO Product term clocking on the outputs. If V is connected to 3.3V the output levels CCO Clock polarity control per logic block meet 3.3V JEDEC standard CMOS levels and are 5V tolerant. These devices require 5V ISR programming. Consistent package/pinout offering across all densities Simplifies design migration Ultra37000V 3.3V Devices Same pinout for 3.3V and 5.0V devices Devices operating with a 3.3V supply require 3.3V on all V CCO pins, reducing the devices power consumption. These Packages devices support 3.3V JEDEC standard CMOS output levels, 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, and are 5V-tolerant. These devices allow 3.3V ISR BGA, and Fine-Pitch BGA packages programming. Lead (Pb)-free packages available Note: 1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V , PCI V = 2V. CC IH Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600 Document : 38-03007 Rev. *E Revised March 7, 2004 + Feedback Ultra37000 CPLD Family Selection Guide 5.0V Selection Guide General Information Device Macrocells Dedicated Inputs I/O Pins Speed (t )Speed (f ) PD MAX CY37032 32 5 32 6 200 CY37064 64 5 32/64 6 200 CY37128 128 5 64/128 6.5 167 CY37192 192 5 120 7.5 154 CY37256 256 5 128/160/192 7.5 154 CY37384 384 5 160/192 10 118 CY37512 512 5 160/192/264 10 118 Speed Bins Device 200 167 154 143 125 100 83 66 CY37032 X X X CY37064 X X X CY37128 X X X CY37192 X X X CY37256 X X X CY37384 X X CY37512 X X X Device-Package Offering and I/O Count 44- 44- 44- 84- 84- 100- 160- 160- 208- 208- 292- 388- Device Lead Lead Lead Lead Lead Lead Lead Lead Lead Lead Lead Lead TQFP PLCC CLCC PLCC CLCC TQFP TQFP CQFP PQFP CQFP PBGA PBGA CY37032 37 37 CY37064 37 37 37 69 69 CY37128 69 69 69 133 CY37192 125 CY37256 133 133 165 197 CY37384 165 197 CY37512 165 165 197 269 3.3V Selection Guide General Information Device Macrocells Dedicated Inputs I/O Pins Speed (t )Speed (f ) PD MAX CY37032V 32 5 32 8.5 143 CY37064V 64 5 32/64 8.5 143 CY37128V 128 5 64/80/128 10 125 CY37192V 192 5 120 12 100 CY37256V 256 5 128/160/192 12 100 CY37384V 384 5 160/192 15 83 CY37512V 512 5 160/192/264 15 83 Document : 38-03007 Rev. *E Page 2 of 64 + Feedback