Am79C972
PCnet-FAST+
Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
DISTINCTIVE CHARACTERISTICS
Integrated Fast Ethernet controller for the Supports PC97, PC98, and Net PC requirements
Peripheral Component Interconnect (PCI) bus
Implements full OnNow features including
32-bit glueless PCI host interface
pattern matching and link status wake-up
Supports PCI clock frequency from DC to
Implements Magic Packet mode
33 MHz independent of network clock
Magic Packet mode and the physical address
Supports network operation with PCI clock
loaded from EEPROM at power up without
from 15 MHz to 33 MHz
requiring PCI clock
High performance bus mastering
Supports PCI Bus Power Management
architecture with integrated Direct Memory
Interface Specification Version 1.0
Access (DMA) Buffer Management Unit for
Supports Advanced Configuration and
low CPU and bus utilization
Power Interface (ACPI) Specification
PCI specification revision 2.1 compliant
Version 1.0
Supports PCI Subsystem/Subvendor ID/
Supports Network Device Class Power
Vendor ID programming through the
Management Specification Version 1.0
EEPROM interface
Large independent internal TX and RX FIFOs
Supports both PCI 3.3-V and 5.0-V signaling
Programmable FIFO watermarks for both
environments
transmit and receive operations
Plug and Play compatible
Receive frame queuing for high latency PCI
Supports an unlimited PCI burst length
bus host operation
Big endian and little endian byte alignments
Programmable allocation of buffer space
supported
between transmit and receive queues
Implements optional PCI power management
Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
event (PME) pin
Media Access Controller (MAC) compliant with
Media Independent Interface (MII) for
IEEE/ANSI 802.3 and Blue Book Ethernet
connecting external 10/100 megabit per second
standards
(Mbps) transceivers
EEPROM interface supports jumperless design
IEEE 802.3-compliant MII
and provides through-chip programming
Intelligent Auto-Poll external PHY status
Supports full programmability of half-/full-
monitor and interrupt
duplex operation for external 10/100 Mbps
Supports both auto-negotiable and non
PHYs through EEPROM mapping
auto-negotiable external PHYs
Programmable PHY reset output pin capable
Supports 10BASE-T, 100BASE-TX/FX,
of resetting external PHY without needing
100BASE-T4, and 100BASE-T2 IEEE 802.3-
buffering
compliant MII PHYs at full- or half-duplex
Integrated oscillator circuit eliminates need for
Supports General Purpose Serial Interface
external crystal
(GPSI) with receive frame tagging support for
Extensive programmable LED status support
internetworking applications
Support for operation in industrial temperature
Full-duplex operation supported in MII and GPSI
range (-40C to +85C)
ports with independent Transmit (TX) and
Receive (RX) channels
Publication# 21485 Rev: E Amendment/0
Issue Date: March 2009
Refer to AMDs Website (www.amd.com) for the latest information. Supports up to 1 megabyte (Mbyte) optional Software compatible with AMD PCnet Family
Boot PROM or Flash for diskless node and LANCE/C-LANCE register and descriptor
application architecture
Look-Ahead Packet Processing (LAPP) data Compatible with the existing PCnet Family
handling technique reduces system overhead driver and diagnostic software
by allowing protocol analysis to begin before
Available in 160-pin PQFP and 176-pin TQFP
the end of a receive frame
packages
Programmable Inter Packet Gap (IPG) to
+3.3 V power supply with 5 V tolerant I/Os
address less network aggressive MAC
enables broad system compatibility
controllers
Extensive programmable internal/external
Offers the Modified Back-Off algorithm to
loopback capabilities
address the Ethernet Capture Effect
Supports patented External Address Detection
IEEE 1149.1-compliant JTAG Boundary Scan
Interface (EADI)
test access port interface and NAND tree test
mode for board-level production connectivity
test
GENERAL DESCRIPTION
The Am79C972 PCnet-FAST+ controller is a highly- test interface for board-level testing is also provided, as
integrated 32-bit full-duplex, 10/100-Megabit per sec- well as a NAND tree test structure for those systems
ond (Mbps) Ethernet controller solution, designed to that cannot support the JTAG interface.
address high-performance system application require-
The Am79C972 PCnet-FAST+ controller is also com-
ments. It is a flexible bus mastering device that can be
pliant with the PC97, PC98, and Net PC specifications.
used in any application, including network-ready PCs
It includes the full implementation of the Microsoft
and bridge/router designs. The bus master architecture
OnNow and ACPI specifications, which are backward
provides high data throughput and low CPU and sys-
compatible with the Magic Packet technology, and is
tem bus utilization. The Am79C972 controller is fabri-
compliant with the PCI Bus Power Management Inter-
cated with advanced low-power 3.3-V CMOS process
face Specification by supporting the four power man-
to provide low operating current for power sensitive ap-
agement states (D0, D1, D2, and D3), the optional
plications.
PME pin, and the necessary configuration and data
The Am79C972 PCnet-FAST+ controller also has sev- registers.
eral enhancements over its predecessor, the
The Am79C972 PCnet-FAST+ controller is ideally
Am79C971 PCnet-FAST device. In addition to integrat-
suited for Network PC (Net PC), motherboard, network
ing the SRAM on chip, it further reduces system imple-
interface card (NIC), and embedded designs. It is avail-
mentation cost by the addition of a new EEPROM
able in a 160-pin Plastic Quad Flat Pack (PQFP) pack-
programmable pin (PHY_RST), an internal oscillator
age and also in a 176-pin Thin Quad Flat Pack (TQFP)
circuit eliminating the need for an external crystal, and
package for form factor sensitive designs.
the integration of the PAL function needed for Magic
Packet application. The PHY_RST pin is implemented The Am79C972 PCnet-FAST+ controller is a complete
to reset the external PHY without increasing the load to Ethernet node integrated into a single VLSI device. It
the PCI bus and to block RST to the PHY when PG contains a bus interface unit, a Direct Memory Access
input is LOW. (DMA) Buffer Management Unit, an ISO/IEC 8802-3
(IEEE 802.3)-compliant Media Access Controller
The 32-bit multiplexed bus interface unit provides a di-
(MAC), a large Transmit FIFO and a large Receive
rect interface to the PCI local bus, simplifying the
FIFO, and an IEEE 802.3-compliant MII. Both IEEE
design of an Ethernet node in a PC system. The
802.3 compliant full-duplex and half-duplex operations
Am79C972 PCnet-FAST+ controller provides the com-
are supported on the MII and GPSI interfaces. 10/100
plete interface to an Expansion ROM or Flash device
Mbps operation is supported through the MII.
allowing add-on card designs with only a single load
per PCI bus interface pin. With its built-in support for The Am79C972 PCnet-FAST+ controller is register
both little and big endian byte alignment, this controller compatible with the LANCE (Am7990) and C-
also addresses non-PC applications. The Am79C972 LANCE (Am79C90) Ethernet controllers, and all
controllers advanced CMOS design allows the bus in- Ethernet controllers in the PCnet Family except
terface to be connected to either a +5-V or a +3.3-V sig- ILACC (Am79C900), including the PCnet-ISA con-
naling environment. A compliant IEEE 1149.1 JTAG troller (Am79C960), PCnet-ISA+ (Am79C961),
2 Am79C972