PRELIMINARY
Am79C976
PCnet-PRO
10/100 Mbps PCI Ethernet Controller
DISTINCTIVE CHARACTERISTICS
Integrated Fast Ethernet controller for the Full-duplex operation supported with
Peripheral Component Interconnect (PCI) bus independent Transmit (TX) and Receive (RX)
channels
32-bit glueless PCI host interface
Includes support for IEEE 802.1Q VLANs
Supports PCI clock frequency from DC to
33 MHz independent of network clock Automatically inserts, deletes, or modifies
VLAN tag
Supports network operation with PCI clock
from 15 MHz to 33 MHz Optionally filters untagged frames
High performance bus mastering
Provides optional flow control features
architecture with integrated Direct Memory
Recognizes and transmits IEEE 802.3x MAC
Access (DMA) Buffer Management Unit for
flow control frames
low CPU and bus utilization
Asserts collision-based back pressure in
PCI specification revision 2.2 compliant
half-duplex mode
Supports PCI Subsystem/Subvendor
Provides internal Management Information
ID/Vendor ID programming through the
Base (MIB) counters for network statistics
EEPROM interface
Supports PC97, PC98, PC99, and Net PC
Supports both PCI 3.3-V and 5.0-V signaling
requirements
environments
Implements full OnNow features including
Plug and Play compatible
pattern matching and link status wake-up
Uses advanced PCI commands (MWI, MRL,
Implements Magic Packet mode
MRM)
Magic Packet mode and the physical address
Optionally supports PCI bursts aligned to
loaded from EEPROM at power up without
cache line boundaries
requiring PCI clock
Supports big endian and little endian byte
Supports PCI Bus Power Management
alignments
Interface Specification Version 1.1
Implements optional PCI power management
Supports Advanced Configuration and
event (PME) pin
Power Interface (ACPI) Specification Version
Supports 40-bit addressing (using PCI Dual
1.0
Address Cycles)
Supports Network Device Class Power
Media Independent Interface (MII) for
Management Specification Version 1.0
connecting external 10/100 megabit per second
Large independent external TX and RX FIFOs
(Mbps) transceivers
Supports up to 4 megabytes (Mbytes)
IEEE 802.3-compliant MII
external SSRAM for RX and TX frame storage
Intelligent Auto-Poll external PHY status
Programmable FIFO watermarks for both
monitor and interrupt
transmit and receive operations
Supports both auto-negotiable and non auto-
Receive frame queuing for high latency PCI
negotiable external PHYs
bus host operation
Supports 10BASE-T, 100BASE-TX/FX,
Programmable allocation of buffer space
100BASE-T4, and 100BASE-T2 IEEE 802.3-
between transmit and receive queues
compliant MII PHYs at full- or half-duplex
This document contains information on a product under development at Advanced Micro Devices. The information Publication# 22929 Rev: E Amendment/0
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
Issue Date: September 2000
product without notice.
Refer to AMDs Website (www.amd.com) for the latest information.P RE L I M INARY
Dual-speed CSMA/CD (10 Mbps and 100 Mbps) Programmable Inter Packet Gap (IPG) to
Media Access Controller (MAC) compliant with address less aggressive network MAC
IEEE/ANSI 802.3 and Blue Book Ethernet controllers
standards
Offers the Modified Back-Off algorithm to
Programmable internal/external loopback address the Ethernet Capture Effect
capabilities
Optionally sends and receives non-standard
Supports patented External Address Detection frames of up to 64K octets in length
Interface (EADI) with receive frame tagging
IEEE 1149.1-compliant JTAG Boundary Scan
support for internetworking applications
test access port interface for board-level
EEPROM interface supports jumperless design production connectivity test
and provides through-chip programming
Provides built-in self test (MBIST) for the
Supports full programmability of all internal external SSRAM
registers through EEPROM mapping
Software compatible with AMD PCnet Family
Programmable PHY reset output pin capable of and LANCE/C-LANCE register and descriptor
resetting external PHY without needing architecture
buffering
Compatible with the existing PCnet Family
Integrated oscillator circuit is controlled by driver and diagnostic software (except for
external crystal statistics)
Extensive programmable LED status support Available in 208-pin PQFP package
Supports up to 16 Mbyte optional Boot PROM or +3.3-V power supply with 5-V tolerant I/Os
Flash for diskless node application enables broad system compatibility
Look-Ahead Packet Processing (LAPP) data
Support for operation in Industrial temperature
handling technique reduces system overhead
range (-40 C to +85 C) available.
by allowing protocol analysis to begin before
the end of a receive frame
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