56 55 54 53 52 51 50 49 25 26 27 28 15 16 17 18 19 20 21 22 23 24 PRODUCT BRIEF CHL8318 DIGITAL MULTI-PHASE BUCK CONTROLLER FEATURES DESCRIPTION Intel VR11.x compliant Digital PWM Controller The CHL8318 is a 8-phase digital synchronous buck controller for core regulation of high-performance INTEL Programmable 1-phase to 8-phase operation VR11.1 and VR11.0 platforms. The CHL8318 is fully Configurable switching frequency from 200 kHz to compliant with VR11.1 including Power Status Indicator 1MHz per phase with accuracy better than 2% (PSI) and for improved light load efficiency and accurate Customized Digital Over-Clocking Features current output (IMON). o Easy-to-use SMBus Gamer command The CHiL CHL8318 includes a customized set of digital o Gamer VID control up to 2.3V, Gamer Vmax, over-clocking features which require no external VID Override or Track, Digital Load-Line Adjust, components. Gaming applications can use the SMBus Gamer OC/OVP, Gamer OFF pin, Gamer OTP interface to place the VRD into Gamer Mode. Gamer Mode CHiL Efficiency Shaping Features features include Extended Gamer VID up to 2.3V with 6.25 mV resolution, Gamer Vmax, CPU VID Override or Track, o Variable Gate Drive Digital Load-Line adjust, Gamer OC/OVP and Gamer OFF o Dynamic Phase Control pin. 1-phase to 4-phase PSI for Light Loads The CHL8318 deploys a number of efficiency shaping Adaptive Transient Algorithm minimizes output bulk features. The CHL8318 can be configured to optimize capacitors MOSFET gate drive versus load current, PSI can be Designed for use with coupled inductors programmed to be up to four phases for optimum light-load Enables Thermal Phase Balancing efficiency, and the controller can autonomously add/drop phases in low-current and mid-current regions to deliver SMBus Fault Indicators: OVP, UVP, OCP, OTP 90+% efficiency across the entire load range. SMBus interface for configuring and monitoring SMBus commands include monitoring input current and power CHiLs unique Adaptive Transient Algorithm, based on non- linear digital PWM algorithms, minimizes output bulk Compatible with CHiL ATL Drivers and tri-state Drivers capacitors. Coupled inductor mode of operation allows two Nine bytes of NVM storage available for customer use phase PSI and add/drop of phases which are 180out of +3.3V supply voltage 0C to 85C Ambient operation phase for further improvement in transient response and form factor. RoHS Compliant, MSL level 1 package CHL8318 supports three NTC temperature sensors to report temperature and trigger VR HOT and OTP faults. Digital thermal balancing allows proportional current imbalance between phases. 48 47 46 45 44 43 RCSP 1 42 IRTN8 The CHL8318 provides extensive OVP, UVP, OCP and OTP RCSM 2 41 ISEN8 fault protection. Device and fault configuration parameters VCC 3 40 VCC are easily defined using the CHiL Intuitive Power Designer VCPU 4 39 PWM8 (IPD) GUI and stored in on-chip non-volatile memory (NVM). CHiL VRTN 5 38 PWM7 CHL8318 SADDR/ 37 6 PWM6 GAMER OFF 56 Pin The 3-pin SMBus interface can be used to monitor a variety 7 8mmx8mm 36 IMON PWM5 of operating parameters on up to seven CHL8318 based QFN RRES 8 35 PWM4 TOP VIEW VRs. The controller includes a unique sensorless and 9 VINSEN 34 PWM3 lossless input current monitoring capability. 10 TSEN1 33 PWM2 GND 11 32 TSEN2 PWM1 TSEN3 12 31 The CHL8318 truly simplifies VRD design and enables NC EN 13 30 VCC fastest time-to-market with its set-and-forget methodology. 14 29 V18A VAR GATE APPLICATIONS Intel VR11.x CPU VRD and VRM DDR Memory High Performance Desktops and Servers Over-clocking and High-Efficiency Applications Figure 1. CHL8318 56 Pin QFN Package Trademarks and registered trademarks are the property of the respective One Highwood Dr ive, Tewksbury, MA 01876 owners. Tel: +1(978)-640-0011 Page 1 of 4 www.chilsemi.com PB0006 Rev. 1.00, October 26, 2009 2009 CHiL Semiconductor Corp. All rights reserved SALERT IRTN1 ISEN1 SDA SCL IRTN2 ISEN2 PSI VID7 IRTN3 VID6 ISEN3 VID5 IRTN4 VID4 ISEN4 VID3 IRTN5 ISEN5 VID2 VID1 IRTN6 ISEN6 VID0 VR READY IRTN7 VR HOT ISEN7CHL8318 PRODUCT BRIEF DIGITAL MULTI-PHASE BUCK CONTROLLER FUNCTIONAL BLOCK DIAGRAM RRES V18A 3.3V VID0 1.8V LDO VID1 Reference VID2 VID3 VID decode and DAC VID4 Digital Processor VID5 Vref VID6 VID7 PID + OVP Controller PWM1 Voltage VCPU Error PWM2 VRTN ADC PWM3 Transient PWM PWM4 ISEN1 Controller Generator IRTN1 PWM5 ISEN2 PWM6 IRTN2 ISEN3 PWM7 IRTN3 PWM8 ISEN4 IRTN4 Channel Current Sense ISEN5 Current IRTN5 ISEN6 Balance IRTN6 ISEN7 IRTN7 ISEN8 IRTN8 RCSP RCSM Monitor TSEN1 ADC VAR GATE TSEN2 OVP TSEN3 VINSEN Oscillator, NVM EN State Control, and Current IMON Monitoring Monitor SADDR/ GAMER OFF PSI SDA SMBus Interface SCL VR Ready GND SALERT VRHOT Figure 2. Functional Block Diagram Page 2 of 4 PB0006 Rev. 1.00, October 26, 2009