Ultra37000 CPLD Family 5 V and 3.3 V ISR High Performance CPLDs 5 V and 3.3 V ISR High Performance CPLDs Features General Description In-System Reprogrammable (ISR) CMOS CPLDs The Ultra37000 family of CMOS CPLDs provides a range of high density programmable logic solutions with unparalleled JTAG interface for reconfigurability system performance. The Ultra37000 family is designed to bring Design changes do not cause pinout changes the flexibility, ease of use, and performance of the 22 V10 to high Design changes do not cause timing changes density CPLDs. The architecture is based on a number of logic High Density blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own product term 32 to 512 macrocells array, product term allocator, and 16 macrocells. The PIM 32 to 264 I/O pins distributes signals from the logic block outputs and all input pins 5 dedicated inputs including 4 clock pins to the logic block inputs. Simple Timing Model All the Ultra37000 devices are electrically erasable and No fanout delays In-System Reprogrammable (ISR), which simplifies both design No expander delays and manufacturing flows, thereby reducing costs. The ISR No dedicated vs. I/O pin delays feature provides the ability to reconfigure the devices without No additional delay through PIM having design changes cause pinout or timing changes. The No penalty for using full 16 product terms Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and No delay for steering or sharing product terms TDO pins, respectively. Because of the superior routability and 3.3 V and 5 V Versions simple timing model of the Ultra37000 devices, ISR allows users 1 to change existing logic designs while simultaneously fixing PCI Compatible pinout assignments and maintaining system performance. Programmable Bus-hold Capabilities on All I/Os The entire family features JTAG for ISR and boundary scan, and Intelligent Product Term Allocator Provides is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Ultra37000 family 0 to 16 product terms to any macrocell features user programmable bus-hold capabilities on all I/Os. Product term steering on an individual basis Product term sharing among local macrocells Ultra37000 5 V Devices Flexible Clocking The Ultra37000 devices operate with a 5 V supply and can 4 synchronous clocks per device support 5 V or 3.3 V I/O levels. V connections provide the CCO Product term clocking capability of interfacing to either a 5 V or 3.3 V bus. By Clock polarity control per logic block connecting the V pins to 5 V the user insures 5V TTL levels CCO on the outputs. If V is connected to 3.3 V the output levels CCO Consistent Package and Pinout Offering across All Densities meet 3.3 V JEDEC standard CMOS levels and are 5 V tolerant. Simplifies design migration These devices require 5 V ISR programming. Same pinout for 3.3 V and 5 V devices Ultra37000V 3.3 V Devices Packages Devices operating with a 3.3 V supply require 3.3 V on all V 44 to 256 pins in PLCC, PQFP, TQFP, and Fine-Pitch BGA CCO pins, reducing the devices power consumption. These devices Packages support 3.3 V JEDEC standard CMOS output levels, and are Pb-free packages available 5V-tolerant. These devices allow 3.3 V ISR programming. Note 1. Due to the 5 V tolerant nature of 3.3 V device I/Os, the I/Os are not clamped to V , PCI V = 2 V. CC IH Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-03007 Rev. *I Revised August 23, 2012Not Recommended for New DesigUltra37000 CPLD Family Contents Logic Block Diagrams ......................................................3 Endurance Characteristics ............................................ 20 Selection Guide ................................................................6 3.3 V Device Maximum Ratings ..................................... 21 5 V Selection Guide .....................................................6 Operating Range ............................................................. 21 3.3 V Selection Guide ..................................................7 3.3 V Device Electrical Characteristics ......................... 21 Pin Configurations ...........................................................8 Inductance ....................................................................... 22 Architecture Overview of Ultra37000 Family ...............13 Capacitance ....................................................................22 Programmable Interconnect Matrix ...........................13 Endurance Characteristics ............................................ 22 Logic Block ................................................................13 AC Test Loads and Waveforms ..................................... 23 Product Term Allocator ..............................................14 Switching Characteristics .............................................. 25 Ultra37000 Macrocell ................................................14 Switching Characteristics .............................................. 27 Clocking .....................................................................16 Switching Waveforms .................................................... 30 Timing Model .............................................................16 Power Consumption ....................................................... 34 JTAG and PCI Standards ...............................................17 Typical 5 V Power Consumption ............................... 34 PCI Compliance ........................................................17 Typical 3.3 V Power Consumption ............................ 37 IEEE 1149.1-compliant JTAG ...................................17 Ordering Information ...................................................... 40 Development Software Support ....................................17 5 V Ordering Information ........................................... 40 Warp ..........................................................................17 3.3 V Ordering Information ........................................ 40 Warp Professional .................................................17 Ordering Code Definitions ......................................... 41 Warp Enterprise .....................................................17 Package Diagrams .......................................................... 42 Third-Party Software .................................................17 Acronyms ........................................................................45 Programming .............................................................17 Document Conventions ................................................. 45 Third-Party Programmers ..........................................18 Units of Measure ....................................................... 45 5 V Device Maximum Ratings ........................................19 Document History Page ................................................. 46 Operating Range .............................................................19 Sales, Solutions, and Legal Information ...................... 50 5 V Device Electrical Characteristics ............................19 Worldwide Sales and Design Support ....................... 50 Inductance .......................................................................20 Products ....................................................................50 Capacitance ....................................................................20 PSoC Solutions ......................................................... 50 Document Number: 38-03007 Rev. *I Page 2 of 50Not Recommended for New Desig