CPLD Family FLASH370 UltraLogic High-Density Flash CPLDs Features General Description Flash erasable CMOS CPLDs LASH The F 370 family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled High density performance. Each member of the family is designed with Cy- 32128 macrocells presss state-of-the-art Flash technology. All of the devices are 32128 I/O pins electrically erasable and reprogrammable, simplifying product inventory and reducing costs. Multiple clock pins LASH The F 370 family is designed to bring the flexibility, ease Bus Hold capabilities on all I/Os and dedicated inputs of use and performance of the 22V10 to high-density CPLDs. High speed The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). t = 8.512 ns PD Each logic block features its own product term array, product t = 57 ns S term allocator array, and 16 macrocells. The PIM distributes t = 67 ns signals from one logic block to another as well as all inputs CO from pins. Fast Programmable Interconnect Matrix (PIM) The family features a wide variety of densities and pin counts Uniform predictable delay, independent of routing to choose from. At each density there are two packaging op- Intelligent product term allocator tions to choose fromone that is I/O intensive and another 016 product terms to any macrocell that is register intensive. For example, the CY7C374 and CY7C375 both feature 128 macrocells. On the CY7C374, Provides product term steering on an individual available in an 84-pin package, half of the macrocells are bur- basis ied and half are available on I/O pins. On the CY7C375 all of Provides product term sharing among local the macrocells are fed to I/O pins and the device is available macrocells Figure 1 in the 160-pin package. shows a block diagram of the CY7C374/5. Doesnt strand macrocells Simple timing model Functional Description No fanout delays Programmable Interconnect Matrix No expander delays The Programmable Interconnect Matrix (PIM) consists of a No dedicated vs. I/O pin delays completely global routing matrix for signals from I/O pins and No additional delay through PIM feedbacks from the logic blocks. The PIM is an extremely ro- bust interconnect that avoids fitting and density limitations. No penalty for using full 16 product terms Routing is automatically accomplished by software and the No delay for steering or sharing product terms propagation delay through the PIM is transparent to the user. Signals from any pin or any logic block can be routed to any or Flexible clocking all logic blocks. 24 clock pins per device Clock polarity control Security bit and user ID supported Packages 44160 pins PLCC, CLCC, PGA, and TQFP packages Table 1. FLASH370 Selection Guide Device Pins Macrocells Dedicated Inputs I/O Pins Flip-Flops Speed (t ) Speed (f ) PD MAX 371 44 32 6 32 44 8.5 143 372 44 64 6 32 76 10 125 373 84 64 6 64 76 10 125 374 84 128 6 64 140 12 100 375 160 128 6 128 140 12 100 Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600 July 20, 2000CPLD Family FLASH370 CLOCK Logic Block Diagram INPUTS INPUTS 2 4 INPUT INPUT/CLOCK MACROCELLS MACROCELLS 4 4 16 I/Os 16 I/Os LOGIC LOGIC BLOCK 36 36 BLOCK I/O I/O I/O I/O 0 15 112 127 A H PIM 16 16 LOGIC LOGIC 16 I/Os 16 I/Os BLOCK 36 36 BLOCK I/O I/O I/O I/O 16 31 96 111 B G 16 16 16 I/Os LOGIC LOGIC 16 I/Os BLOCK 36 BLOCK I/O I/O 36 I/O I/O 32 47 80 95 C F 16 16 LOGIC LOGIC 16 I/Os LOGIC 16 I/Os BLOCK BLOCK 36 36 I/O I/O I/O I/O 48 63 64 79 D E 16 16 64 64 Figure 1. CY7C375 Block Diagram Logic Block Functional Description (continued) The logic block is the basic building block of the FLASH370 The inputs to the PIM consist of all I/O and dedicated input pins architecture. It consists of a product term array, an intelligent and all macrocell feedbacks from within the logic blocks. The product-term allocator, 16 macrocells, and a number of I/O number of PIM inputs increases with pincount and the number cells. The number of I/O cells varies depending on the device of logic blocks. The outputs from the PIM are signals routed to used. the appropriate logic block(s). Each logic block receives 36 There are two types of logic blocks in the FLASH370 family. The inputs from the PIM and their complements, allowing for 32-bit first type features an equal number (16) of I/O cells and mac- operations to be implemented in a single pass through the rocells and is shown in Figure 2. This architecture is best for device. The wide number of inputs to the logic block also im- I/O-intensive applications. The second type of logic block fea- proves the routing capacity of the FLASH370 family. tures a buried macrocell along with each I/O macrocell. In oth- An important feature of the PIM involves timing. The propaga- er words, in each logic block, there are eight macrocells that tion delay through the PIM is accounted for in the timing spec- are connected to I/O cells and eight macrocells that are inter- ifications for each device. There is no additional delay for trav- nally fed back to the PIM only. This organization is designed eling through the PIM. In fact, all inputs travel through the PIM. for register-intensive applications and is displayed in Figure 3. Likewise, there are no route-dependent timing parameters on Note that at each FLASH370 density (except the smallest), an the FLASH370 devices. The worst-case PIM delays are incor- I/O intensive and a register-intensive device is available. porated in all appropriate FLASH370 specifications. Product Term Array Routing signals through the PIM is completely invisible to the user. All routing is accomplished by softwareno hand routing Each logic block features a 72 x 86 programmable product is necessary. Warp and third-party development packages term array. This array is fed with 36 inputs from the PIM, which automatically route designs for the FLASH370 family in a matter originate from macrocell feedbacks and device pins. Active of minutes. Finally, the rich routing resources of the FLASH370 LOW and active HIGH versions of each of these inputs are family accommodate last minute logic changes while maintain- generated to create the full 72-input field. The 86 product ing fixed pin assignments. terms in the array can be created from any of the 72 inputs. 2