CY7C601xx/CY7C602xx enCoRe II Low-Voltage Microcontroller SPI serial communication 1. Features Master or slave operation enCoRe II low-voltage (enCoRe II LV) enhanced Configurable up to 2 Mbit per second transfers component reduction Supports half-duplex single-data line mode for optical Internal crystalless oscillator with support for optional sensors external clock or external crystal or resonator 2-channel 8-bit or 1-channel 16-bit capture timer registers, Configurable I/O for real world interface without external which store both rising and falling edge times components Two registers each for two input pins Enhanced 8-bit microcontroller Separate registers for rising and falling edge capture Harvard architecture Simplifies interface to radio frequency (RF) inputs for wireless M8C CPU speed up to 12 MHz or sourced by an external applications crystal, resonator, or clock signal Internal low-power wakeup timer during suspend mode Internal memory Periodic wakeup with no external components 256 bytes of random access memory (RAM) Programmable interval timer interrupts 8 KB of flash including electrically erasable read only memory (EEROM) emulation Reduced RF emissions at 27 MHz and 96 MHz Low power consumption Watchdog timer (WDT) Typically 2.25 mA at 3 MHz Low-voltage detection (LVD) with user-selectable threshold 5 A sleep voltages In-system reprogrammability Improved output drivers to reduce electromagnetic interference Enables easy firmware update (EMI) General-purpose I/O (GPIO) ports Operating voltage from 2.7 V to 3.6 V DC Up to 36 GPIO pins 2-mA source current on all GPIO pins Operating temperature from 0 C to 70 C Configurable 8 or 50 mA per pin current sink on designated Available in 40-pin plastic dual inline package (PDIP), 24-pin pins small outline integrated circuit (SOIC), 24-pin quad small Each GPIO port supports high-impedance inputs, outline package (QSOP) and shrink small outline package configurable pull-up, open drain output, complementary (SSOP), 48-pin SSOP metal oxide semiconductor (CMOS), and transistor-transistor logic (TTL) inputs, and CMOS output Advanced development tools based on Cypress PSoC tools Maskable interrupts on all I/O pins Industry-standard programmer support 2. Logic Block Diagram Wakeup 4 SPI/GPIO 16 GPIO Interrupt 16 Extended Timer Pins Pins Control I/O Pins Internal 12 MHz Oscillator Capture RAM Flash M8C CPU Clock 12-bit Timer Timers 256 Byte 8 KB Control Crystal Oscillator Watchdog CY7C601xx only POR / Timer Low-Voltage Detect Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-16016 Rev. *K Revised September 11, 2014 V DDCY7C601xx/CY7C602xx 3. Contents Applications ......................................................................3 Low-Voltage Detect Control ......................................... 35 Introduction .......................................................................3 POR Compare State ................................................. 36 Conventions ......................................................................3 ECO Trim Register .................................................... 36 Pinouts ..............................................................................4 General-Purpose I/O Ports ............................................. 37 Pin Assignments ..........................................................5 Port Data Registers ................................................... 37 Register Summary ............................................................7 GPIO Port Configuration ........................................... 38 CPU Architecture ..............................................................9 Serial Peripheral Interface (SPI) .................................... 45 CPU Registers ...................................................................9 SPI Data Register ...................................................... 46 Flags Register .............................................................9 SPI Configure Register ............................................. 46 Addressing Modes .....................................................11 SPI Interface Pins ...................................................... 48 Instruction Set Summary ...............................................13 Timer Registers .............................................................. 48 Memory Organization .....................................................15 Registers ...................................................................48 Flash Program Memory Organization .......................15 Interrupt Controller ......................................................... 55 Data Memory Organization .......................................16 Architectural Description ........................................... 56 Flash ..........................................................................16 Interrupt Processing ..................................................56 SROM ........................................................................16 Interrupt Latency ....................................................... 56 SROM Function Descriptions ....................................17 Interrupt Registers ..................................................... 57 SROM Table Read Description .................................20 Absolute Maximum Ratings .......................................... 60 Clocking ..........................................................................22 DC Characteristics .................................................... 60 Trim Values for the IOSCTR Register .......................22 AC Characteristics .................................................... 61 Clock Architecture Description ..................................23 Ordering Information ...................................................... 64 CPU Clock During Sleep Mode .................................30 Package Handling ........................................................... 64 Reset ................................................................................31 Package Diagrams .......................................................... 65 Power On Reset ........................................................32 Document History Page ................................................. 67 Watchdog Timer Reset ..............................................32 Sales, Solutions, and Legal Information ...................... 69 Sleep Mode ......................................................................32 Sleep Sequence ........................................................33 Wakeup Sequence ....................................................34 Document Number: 38-16016 Rev. *K Page 2 of 69