CY7C66013C/CY7C66113C Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub Improved output drivers to reduce electromagnetic interference Features (EMI) Full speed USB peripheral microcontroller with an integrated Operating voltage from 4.0 V5.5 V DC USB hub Operating temperature from 0 C70 C Well suited for USB compound devices such as a keyboard hub function CY7C66013C available in 48-pin SSOP (-PVXC) packages 8-bit USB optimized microcontroller CY7C66113C available in 56-pin QFN or 56-pin SSOP (-PVXC) Harvard architecture packages 6 MHz external clock source Industry standard programmer support 12 MHz internal CPU clock 48 MHz internal Hub clock Functional Overview Internal memory 256 bytes of RAM The CY7C66013C and CY7C66113C are compound devices with a full speed USB microcontroller in combination with a USB 8 kB of PROM hub. Each device is suited for combination peripheral functions 2 Integrated Master and Slave I C compatible controller with hubs such as a keyboard hub function. The 8-bit one time (100 kHz) enabled through General Purpose I/O (GPIO) pins programmable microcontroller with a 12 Mbps USB Hub supports as many as four downstream ports. Hardware Assisted Parallel Interface (HAPI) for data transfer to external devices GPIO I/O ports The CY7C66013C features 29 GPIO pins to support USB and Three GPIO ports (Port 0 to 2) capable of sinking 8 mA per other applications. The I/O pins are grouped into four ports pin (typical) (P0 7:0 , P1 7:0 , P2 7:0 , P3 4:0 ) where each port is configured An additional GPIO port (Port 3) capable of sinking 12 mA as inputs with internal pull ups, open drain outputs, or traditional per pin (typical) for high current requirements: LEDs CMOS outputs. Ports 0 to 2 are rated at 8 mA per pin (typical) Higher current drive achievable by connecting multiple GPIO sink current. Port 3 pins are rated at 12 mA per pin (typical) sink pins together to drive a common output current, which allows these pins to drive LEDs. Multiple GPIO Each GPIO port is configured as inputs with internal pull ups pins are connected together to drive a single output for more or open drain outputs or traditional CMOS outputs drive current capacity. Additionally, each I/O pin is used to A Digital to Analog Conversion (DAC) port with generate a GPIO interrupt to the microcontroller. All of the GPIO programmable current sink outputs is available on the interrupts all share the same GPIO interrupt vector. CY7C66113C device The CY7C66113C has 31 GPIO pins (P0 7:0 , P1 7:0 , P2 7:0 , Maskable interrupts on all I/O pins P3 6:0 ). 12-bit free running timer with one microsecond clock ticks DAC Watchdog Timer (WDT) The CY7C66113C has an additional port P4 7:0 that features an Internal Power on Reset (POR) additional eight programmable sink current I/O pins (DAC). Every DAC pin includes an integrated 14 k pull up resistor. USB Specification compliance When a 1 is written to a DAC I/O pin, the output current sink is Conforms to USB Specification, Version 1.1 disabled and the output pin is driven HIGH by the internal pull up Conforms to USB HID Specification, Version 1.1 resistor. When a 0 is written to a DAC I/O pin, the internal pull Supports one or two device addresses with up to five user up is disabled and the output pin provides the programmed configured endpoints amount of sink current. A DAC I/O pin is used as an input with Up to two 8-byte control endpoints an internal pull up by writing a 1 to the pin. Up to four 8-byte data endpoints The sink current for each DAC I/O pin is individually programmed Up to two 32-byte data endpoints to one of sixteen values using dedicated Isink registers. DAC bits Integrated USB transceivers DAC 1:0 is used as high current outputs with a programmable Supports four downstream USB ports sink current range of 3.2 to 16 mA (typical). DAC bits DAC 7:2 GPIO pins provide individual power control outputs for each have a programmable current sink range of 0.2 to 1.0 mA downstream USB port (typical). Multiple DAC pins are connected together to drive a GPIO pins provide individual port over current inputs for each single output that requires more sink current capacity. Each I/O downstream USB port pin is used to generate a DAC interrupt to the microcontroller. Also, the interrupt polarity for each DAC I/O pin is individually programmable. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-08024 Rev. *I Revised April 12, 2017CY7C66013C/CY7C66113C Clock Interrupts The microcontroller uses an external 6 MHz crystal and an The microcontroller supports eleven maskable interrupts in the internal oscillator to provide a reference to an internal PLL based vectored interrupt controller. Interrupt sources include the 128 s clock generator. This technology allows the customer application (bit 6) and 1.024 ms (bit 9) outputs from the free-running timer, to use an inexpensive 6 MHz fundamental crystal that reduces five USB endpoints, the USB hub, the DAC port, the GPIO ports, 2 the clock related noise emissions (EMI). A PLL clock generator and the I C compatible master mode interface. The timer bits provides the 6, 12, and 48 MHz clock signals for distribution cause an interrupt (if enabled) when the bit toggles from LOW 0 within the microcontroller. to HIGH 1. The USB endpoints interrupt after the USB host has written data to the endpoint FIFO or after the USB controller Memory sends a packet to the USB host. The DAC ports have an additional level of masking that allows the user to select which The CY7C66013C and CY7C66113C have 8 kB of PROM. DAC inputs causes a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs causes a GPIO Power on Reset, Watchdog, and Free Running Timer interrupt. For additional flexibility, the input transition polarity that These parts include POR logic, a WDT, and a 12-bit free-running causes an interrupt is programmable for each pin of the DAC timer. The POR logic detects when power is applied to the port. Input transition polarity is programmed for each GPIO port device, resets the logic to a known state, and begins executing as part of the port configuration. The interrupt polarity can be instructions at PROM address 0x0000. The WDT is used to rising edge (0 to 1) or falling edge (1 to 0). ensure that the microcontroller recovers after a period of inactivity. The firmware may become inactive for a variety of USB reasons, including errors in the code or a hardware failure such The CY7C66013C and CY7C66113C include an integrated USB as waiting for an interrupt that never occurs. Serial Interface Engine (SIE) that supports the integrated 2 peripherals and the hub controller function. The hardware I C and HAPI Interface supports up to two USB device addresses with one device The microcontroller communicates with external electronics address for the hub (two endpoints) and a device address for a 2 through the GPIO pins. An IC compatible interface compound device (three endpoints). The SIE allows the USB accommodates a 100 kHz serial link with an external device. host to communicate with the hub and functions integrated into There is also a HAPI to transfer data to an external device. the microcontroller. The part includes a 1:4 hub repeater with one upstream port and four downstream ports. The USB Hub allows Timer power management control of the downstream ports by using The free-running 12-bit timer clocked at 1 MHz provides two GPIO pins assigned by the user firmware. The user has the interrupt sources, 128 s and 1.024 ms. The timer is used to option of ganging the downstream ports together with a single measure the duration of an event under firmware control by pair of power management pins, or providing power reading the timer at the start of the event and after the event is management for each port with four pairs of power management complete. The difference between the two readings indicates the pins. duration of the event in microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to try to compensate if the upper four bits increment immediately after the lower eight bits are read. Document Number: 38-08024 Rev. *I Page 2 of 61