CY8C20236A Automotive CapSense Applications Automotive CapSense Applications Versatile analog mux Features Common internal analog bus Automotive Electronics Council (AEC) Q100 qualified Simultaneous connection of I/O High power supply rejection ratio (PSRR) comparator Operating Range: 1.71 V to 5.5 V Low-dropout voltage regulator for all analog resources Low power CapSense block Configurable capacitive sensing elements Additional system resources 2 Supports SmartSense I C Slave: Supports a combination of CapSense buttons, sliders, Selectable to 50 kHz, 100 kHz, or 400 kHz touchpads, touchscreens, and proximity sensors No clock stretching (under most conditions) Powerful Harvard-architecture processor Implementation during sleep modes with less than 100 A M8C CPU speed can be up to 24 MHz or sourced by an Hardware address validation external crystal, resonator, or clock signal SPI master and slave: Configurable 46.9 kHz to 12 MHz Low power at high speed Three 16-bit timers Interrupt controller Watchdog and sleep timers Temperature range: 40 C to +85 C Internal voltage reference Flexible on-chip memory Integrated supervisory circuit Two program/data storage size options: 8 to 10-bit incremental analog-to-digital converter (ADC) CY8C20x36A: 8 KB flash/1 KB SRAM Two general-purpose high speed, low power analog 1,000 flash erase/write cycles comparators Partial flash updates Complete development tools Flexible protection modes Free development tool (PSoC Designer) In-system serial programming (ISSP) Full-featured, in-circuit emulator (ICE) and programmer Precision, programmable clocking Full-speed emulation Internal main oscillator (IMO): 6/12/24 MHz 5% Complex breakpoint structure Internal low speed oscillator (ILO) at 32 kHz for watchdog 128 KB trace memory and sleep timers Package options Precision 32 kHz oscillator for optional external crystal Programmable pin configurations CY8C20x36A:16-pin QFN (3 3 0.6 mm) Up to 36 general-purpose I/Os (GPIOs) (depending on package) Dual mode GPIO: All GPIOs support digital I/O and analog inputs 25-mA sink current on each GPIO 120 mA total sink current on all GPIOs Pull-up, high Z, open-drain modes on all GPIOs CMOS drive mode 5 mA source current on ports 0 and 1 and 1 mA on ports 2, 3, and 4 20 mA total source current on all GPIOs Selectable, regulated digital I/O on port 1 Configurable input threshold on port 1 Hot-swap capability on all Port 1 GPIO Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-63115 Rev. *D Revised September 5, 2017 CY8C20236A Logic Block Diagram 1.8/2.5/3V PWRSYS 1 Port 4 Port 3 Port 2 Port 1 Port 0 LDO (Regulator) PSoC CORE SYSTEM BUS Global Analog Interconnect 1K/2K 8K/32K Flash Supervisory ROM (SROM) SRAM Nonvolatile Memory Interrupt Sleep and Controller CPU Core (M8C) Watchdog 6/12/24 MHz Internal Main Oscillator Internal Low Speed Oscillator (ILO) (IMO) Multiple Clock Sources CAPSENSE Analog Reference SYSTEM CapSense Module Two Analog Comparators Mux SYSTEM BUS Internal POR SPI Three 16-Bit I2C System Digital Voltage and Master/ Programmable Slave Resets Clocks References LVD Slave Timers SYSTEM RESOURCES Note 1. Internal voltage regulator for internal circuitry. Document Number: 001-63115 Rev. *D Page 2 of 29