CY8C20XX6A/S 1.8 V Programmable CapSense Controller with SmartSense Auto-tuning 133 Buttons, 06 Sliders 1.8 V Programmable CapSense Controller with SmartSense Auto-tuning 133 Buttons, 06 Sliders Versatile Analog functions Features Internal analog bus supports connection of multiple sensors Low power CapSense block with SmartSense Auto-tuning to form ganged proximity sensor Internal Low-Dropout voltage regulator for high power supply Patented CSA EMC, CSD sensing algorithms rejection ratio (PSRR) SmartSense EMC Auto-Tuning Sets and maintains optimal sensor performance during run Full-Speed USB time 12 Mbps USB 2.0 compliant Eliminates system tuning during development and Additional system resources production I2C Slave: Compensates for variations in manufacturing process Low Selectable to 50 kHz, 100 kHz, or 400 kHz average power consumption 28 A/sensor in run time Configurable up to 12 MHz SPI master and slave (wake-up and scan once every 125 ms) Three 16-bit timers Powerful Harvard-architecture processor Watchdog and sleep timers M8C CPU with a max speed of 24 MHz Integrated supervisory circuit Operating Range: 1.71 V to 5.5 V 10-bit incremental analog-to-digital converter (ADC) with internal voltage reference Standby Mode 1.1 A (Typ) Two general-purpose high speed, low power analog Deep Sleep 0.1 A (Typ) comparators Operating Temperature range: 40 C to +85 C Complete development tools Flexible on-chip memory Free development tool (PSoC Designer) 8 KB flash, 1 KB SRAM Sensor and Package options 16 KB flash, 2 KB SRAM 10 Sensors QFN 16, 24 32 KB flash, 2 KB SRAM 16 Sensors QFN 24 Read while Write with EEPROM emulation 22 / 25 Sensors QFN 32 50,000 flash erase/write cycles 24 Sensors - WLCSP 30 In-system programming simplifies manufacturing process 31 Sensors SSOP 48 Four Clock Sources 33 Sensors QFN 48 Internal main oscillator (IMO): 6/12/24 MHz Internal low-speed oscillator (ILO) at 32 kHz for watchdog and sleep timers External 32 KHz Crystal Oscillator External Clock Input Programmable pin configurations Up to 36 general-purpose I/Os (GPIOs) configurable as buttons or sliders Dual mode GPIO (Analog inputs and Digital I/O supported) High sink current of 25 mA per GPIO Max sink current 120 mA for all GPIOs Source Current 5 mA on ports 0 and 1 1 mA on ports 2,3 and 4 Configurable internal pull-up, high-Z and open drain modes Selectable, regulated digital I/O on port 1 Configurable input threshold on port 1 Errata: For information on silicon errata, see Errata on page 46. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-54459 Rev. *Y Revised May 18, 2017 CY8C20XX6A/S Logic Block Diagram 1 1.8/2.5/3V PWRSYS Port 4 Port 3 Port 2 Port 1 Port 0 LDO (Regulator) PSoC CORE SYSTEM BUS Global Analog Interconnect 1K/2K 8K/16K/32K Flash SRAM Supervisory ROM (SROM) Nonvolatile Memory Interrupt Sleep and Controller CPU Core (M8C) Watchdog 6/12/24 MHz Internal Main Oscillator Internal Low Speed Oscillator (ILO) (IMO) Multiple Clock Sources CAPSENSE Analog Reference SYSTEM CapSense Module Two Analog Comparators Mux SYSTEM BUS Internal POR SPI Three 16-Bit I2C System Digital USB Voltage and Master/ Programmable Slave Resets Clocks References LVD Slave Timers SYSTEM RESOURCES Note 1. Internal voltage regulator for internal circuitry Document Number: 001-54459 Rev. *Y Page 2 of 53