CY8C21x34B PSoC Programmable System-on-Chip CapSense Controller with SmartSense Auto-tuning 121 Buttons, 04 Sliders, Proximity PSoC Programmable System-on-Chip CapSense Controller with SmartSense Auto-tuning 121 Buttons, 04 Sliders, Proximity Flexible on-chip memory Features 8-KB Flash /512-B SRAM Advanced CapSense block with SmartSense Auto-Tuning 50,000 erase/write cycles Patented CSD sensing algorithm In-system serial programming (ISSP) SmartSense EMC Auto-Tuning Partial flash updates Sets and maintains optimal sensor performance during run Flexible protection modes time EEPROM emulation in flash Eliminates system tuning during development and Complete development tools production Free development software (PSoC Designer) Compensates for variations in manufacturing process Full-featured, in-circuit emulator (ICE) and programmer Driven shield Full-speed emulation Delivers best-in class water tolerant designs Complex breakpoint structure Robust proximity sensing in the presence of metal objects 128-KB trace memory Supports longer trace lengths Precision, programmable clocking 1 Powerful Harvard-architecture processor Internal 2.5% 24- / 48-MHz main oscillator M8C processor speeds up to 24 MHz Internal oscillator for watchdog and sleep Low power at high speed Programmable pin configurations Operating voltage: 2.4 V to 5.25 V 25-mA sink, 10-mA source on all GPIOs Operating voltages down to 1.0 V using on-chip switch mode Pull-up, pull-down, high-Z, strong, or open-drain drive modes pump (SMP) on all GPIOs Industrial temperature range: -40 C to 85 C Up to eight analog inputs on GPIOs Advanced peripherals (PSoC blocks) Configurable interrupt on all GPIOs Four analog Type E PSoC blocks provide: Versatile analog mux Two comparators with digital-to-analog converter (DAC) Common internal analog bus references Simultaneous connection of I/O combinations Single or dual 10-bit 28 channel analog-to-digital Capacitive sensing application capability converters (ADC) Additional system resources Four digital PSoC blocks provide: 2 2 I C master, slave, and multi-master to 400 kHz 8- to 32-bit timers, counters, and pulse width modulators (PWMs) Watchdog and sleep timers User-configurable low-voltage detection (LVD) Cyclical redundancy check (CRC) and pseudo random sequence (PRS) modules Integrated supervisory circuit On-chip precision voltage reference Full-duplex universal asynchronous receiver transmitter (UART), serial peripheral interface (SPI) master or slave Package options Connectable to all general purpose I/O (GPIO) pins 16-pin SOIC Implement a combination up to 21 buttons or 4 sliders using 20-pin, 28-pin, 56-pin SSOP 4 analog blocks and 3 digital blocks 32-pin QFN Complex peripherals by combining blocks Errata: For information on silicon errata, see Errata on page 48. Details include trigger conditions, devices affected, and proposed workaround. Notes 1. Errata: The worst case IMO frequency deviation when operated below 0 C and above +70 C and within the upper and lower datasheet temperature range is 5%. 2 2 2. Errata: The I C block exhibits occasional data and bus corruption errors when the I C master initiates transactions while the device is transitioning in to or out of sleep mode. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-67345 Rev. *H Revised January 3, 2018 CY8C21x34B Logic Block Diagram Document Number: 001-67345 Rev. *H Page 2 of 52