PSoC Mixed Signal Array Final Data Sheet CY8C22113 and CY8C22213 Features Powerful Harvard Architecture Processor Precision, Programmable Clocking Additional System Resources 2 M8C Processor Speeds to 24 MHz Internal 2.5% 24/48 MHz Oscillator I C Slave, Master, and Multi-Master to Low Power at High Speed High-Accuracy 24 MHz with Optional 32.768 400 kHz kHz Crystal and PLL 3.0 to 5.25 V Operating Voltage Watchdog and Sleep Timers Optional External Oscillator, up to 24 MHz Industrial Temperature Range: -40C to +85C User-Configurable Low Voltage Detection Internal Oscillator for Watchdog and Sleep Integrated Supervisory Circuit Advanced Peripherals (PSoC Blocks) On-Chip Precision Voltage Reference Flexible On-Chip Memory 3 Rail-to-Rail Analog PSoC Blocks Provide: 2K Bytes Flash Program Storage 50,000 - Up to 14-Bit ADCs Complete Development Tools Erase/Write Cycles - Up to 9-Bit DACs Free Development Software 256 Bytes SRAM Data Storage (PSoC Designer) - Programmable Gain Amplifiers In-System Serial Programming (ISSP) Full-Featured, In-Circuit Emulator and - Programmable Filters and Comparators Partial Flash Updates Programmer 4 Digital PSoC Blocks Provide: Flexible Protection Modes Full Speed Emulation - 8- to 32-Bit Timers, Counters, and PWMs EEPROM Emulation in Flash Complex Breakpoint Structure - CRC and PRS Modules 128K Bytes Trace Memory Programmable Pin Configurations - Full-Duplex UART 25 mA Sink on all GPIO - SPI Masters or Slaves Pull up, Pull down, High Z, Strong, or Open - Connectable to all GPIO Pins Drain Drive Modes on all GPIO Complex Peripherals by Combining Blocks Up to 8 Analog Inputs on GPIO One 30 mA Analog Outputs on GPIO Configurable Interrupt on all GPIO Analog PSoC Functional Overview Port 1 Port 0 Drivers PSoC CORE The PSoC family consists of many Mixed Signal Array with On-Chip Controller devices. These devices are designed to SYSTEM BUS replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC Global Digital Interconnect Global Analog Interconnect devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture SRAM SROM Flash 2K allows the user to create customized peripheral configurations 256 Bytes that match the requirements of each individual application. Sleep and CPU Core (M8C) Interrupt Watchdog Additionally, a fast CPU, Flash program memory, SRAM data Controller memory, and configurable IO are included in a range of conve- Multiple Clock Sources nient pinouts and packages. (Includes IMO, ILO, PLL, and ECO) The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System, DIGITAL SYSTEM ANALOG SYSTEM and System Resources. Configurable global busing allows all Analog Analog the device resources to be combined into a complete custom Digital Ref Block system. The PSoC CY8C22x13 family can have up to two IO Block Array Array ports that connect to the global digital and analog interconnects, (1 Row, Analog (1 Column, providing access to 4 digital blocks and 3 analog blocks. 4 Blocks) Input 3 Blocks) Muxing The PSoC Core The PSoC Core is a powerful engine that supports a rich fea- ture set. The core includes a CPU, memory, clocks, and config- POR and LVD Internal Digital urable GPIO (General Purpose IO). 2 Decimator I C Voltage Clocks System Resets Ref. The M8C CPU core is a powerful processor with speeds up to SYSTEM RESOURCES 24 MHz, providing a four MIPS 8-bit Harvard architecture micro- June 2004 Cypress MicroSystems, Inc. 2004 Document No. 38-12009 Rev. *E 1Row Output Configuration Digital Clocks From Core CY8C22x13 Final Data Sheet PSoC Overview processor. The CPU utilizes an interrupt controller with 10 vec- Digital peripheral configurations include those listed below. tors, to simplify programming of real time embedded events. PWMs (8 to 32 bit) Program execution is timed and protected using the included PWMs with Dead band (8 to 32 bit) Sleep and Watch Dog Timers (WDT). Counters (8 to 32 bit) Memory encompasses 2 KB of Flash for program storage, 256 Timers (8 to 32 bit) bytes of SRAM for data storage, and up to 2 KB of EEPROM UART 8-bit with selectable parity (up to 1) emulated using the Flash. Program Flash utilizes four protec- tion levels on blocks of 64 bytes, allowing customized software SPI master and slave (up to 1) IP protection. I2C slave and master (1 available as a System Resource) The PSoC device incorporates flexible internal clock genera- Cyclical Redundancy Checker/Generator (8 to 32 bit) tors, including a 24 MHz IMO (internal main oscillator) accurate IrDA (up to 1) to 2.5% over temperature and voltage. The 24 MHz IMO can Pseudo Random Sequence Generators (8 to 32 bit) also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for The digital blocks can be connected to any GPIO through a the Sleep timer and WDT. If crystal accuracy is desired, the series of global buses that can route any signal to any pin. The ECO (32.768 kHz external crystal oscillator) is available for use buses also allow for signal multiplexing and for performing logic as a Real Time Clock (RTC) and can optionally generate a crys- operations. This configurability frees your designs from the con- tal-accurate 24 MHz system clock using a PLL. The clocks, straints of a fixed peripheral controller. together with programmable clock dividers (as a System Digital blocks are provided in rows of four, where the number of Resource), provide the flexibility to integrate almost any timing blocks varies by PSoC device family. This allows you the opti- requirement into the PSoC device. mum choice of system resources for your application. Family PSoC GPIOs provide connection to the CPU, digital and analog resources are shown in the table titled PSoC Device Charac- resources of the device. Each pins drive mode may be selected teristics on page 3. from eight options, allowing great flexibility in external interfac- ing. Every pin also has the capability to generate a system inter- The Analog System rupt on high level, low level, and change from last read. The Analog System is composed of 3 configurable blocks, each comprised of an opamp circuit allowing the creation of complex The Digital System analog signal flows. Analog peripherals are very flexible and The Digital System is composed of 4 digital PSoC blocks. Each can be customized to support specific application requirements. block is an 8-bit resource that can be used alone or combined Some of the more common PSoC analog functions (most avail- with other blocks to form 8, 16, 24, and 32-bit peripherals, which able as user modules) are listed below. are called user module references. Analog-to-digital converters (one with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Port 1 Port 0 Filters (two pole band-pass, low-pass, and notch) Amplifiers (one with selectable gain to 48x) To System Bus Comparators (one with 16 selectable thresholds) To Analog System DACs (one with 6- to 9-bit resolution) Multiplying DACs (one with 6- to 9-bit resolution) DIGITAL SYSTEM High current output drivers (one with 30 mA drive as a Core Digital PSoC Block Array Resource) 1.3V reference (as a System Resource) Row 0 8 4 8 Many other topologies possible 8 8 DBB00 DBB01 DCB02 DCB03 4 GIE 7:0 GOE 7:0 Global Digital Interconnect GIO 7:0 GOO 7:0 Digital System Block Diagram June 3, 2004 Document No. 38-12009 Rev. *E 2 Row Input Configuration