CY8C24X93
PSoC Programmable System-on-Chip
PSoC Programmable System-on-Chip
Versatile Analog functions
Features
Internal Low-Dropout voltage regulator for high power supply
Powerful Harvard-architecture processor rejection ratio (PSRR)
M8C CPU with a max speed of 24 MHz
Full-Speed USB
Operating Range: 1.71 V to 5.5 V 12 Mbps USB 2.0 compliant
Eight unidirectional endpoints
Standby Mode 1.1 A (Typ)
One bidirectional endpoint
Deep Sleep 0.1 A (Typ)
Dedicated 512 byte SRAM
Operating Temperature range: 40 C to +85 C
No external crystal required
Flexible on-chip memory
Additional system resources
8 KB flash, 1 KB SRAM
I2C Slave:
16 KB flash, 2 KB SRAM
Selectable to 50 kHz, 100 kHz, or 400 kHz
32 KB flash, 2 KB SRAM
Configurable up to 12 MHz SPI master and slave
Read while Write with EEPROM emulation
Three 16-bit timers
50,000 flash erase/write cycles
Watchdog and sleep timers
In-system programming simplifies manufacturing process
Integrated supervisory circuit
Four Clock Sources
10-bit incremental analog-to-digital converter (ADC) with
internal voltage reference
Internal main oscillator (IMO): 6/12/24 MHz
Two general-purpose Comparators
Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
3 Voltage References (0.8 V, 1 V, 1.2 V)
External 32 KHz Crystal Oscillator
Any pin to either comparator inputs
External Clock Input
Low-power operation at 10 A
Programmable pin configurations One 8-bit IDAC with full scale range of 512 A
One 8-bit Software PWM
Up to 36 general purpose dual mode GPIO (Analog inputs
and Digital I/O supported)
Development Platform
High sink current of 25 mA per GPIO
PSoC Designer IDE
Max sink current 120 mA for all GPIOs
GPIOs and Package options
Source Current
13 GPIOs - QFN 16
5 mA on ports 0 and 1
28 GPIOs - QFN 32
1 mA on ports 2,3 and 4
34 GPIOs - QFN 48
Configurable internal pull-up, high-Z and open drain modes
36 GPIOs - QFN 48
Selectable, regulated digital I/O on port 1
Configurable input threshold on port 1
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-86894 Rev. *B Revised May 24, 2013CY8C24X93
Logic Block Diagram
[1]
1.8/2.5/3V
PWRSYS
Port 4 Port 3 Port 2 Port 1 Port 0
LDO (Regulator)
PSoC CORE
SYSTEM BUS
Global Analog Interconnect
1K/2K
8K/16K/32K Flash
Supervisory ROM (SROM)
SRAM
Nonvolatile Memory
Interrupt
Sleep and
Controller CPU Core (M8C)
Watchdog
6/12/24 MHz Internal Main Oscillator
Internal Low Speed Oscillator (ILO)
(IMO)
Multiple Clock Sources
Analog
ANALOG ADC
Reference
SYSTEM
Two
Comparators
IDAC Analog Mux
SYSTEM BUS
Internal POR SPI
Three 16-Bit
I2C System Digital
USB Voltage and Master/
Programmable
Slave Resets Clocks
References LVD Slave
Timers
SYSTEM RESOURCES
Note
1. Internal voltage regulator for internal circuitry.
Document Number: 001-86894 Rev. *B Page 2 of 65