CY8C24633 PSoC Programmable System-on-Chip PSoC Programmable System-on-Chip Flexible on-chip memory Features 8K flash program storage 50,000 erase/write cycles Powerful Harvard-architecture processor 256 bytes SRAM data storage M8C processor speeds to 24 MHz In-System Serial Programming (ISSP) 8 8 multiply, 32-bit accumulate Partial flash updates low Power at High Speed Flexible protection modes 3.0 to 5.25 V operating voltage EEPROM emulation in flash industrial temperature range: 40 C to +85 C Programmable pin configurations Advanced peripherals (PSoC Blocks) 25 mA sink on all GPIO Four Rail-to-Rail analog PSoC blocks provide: Pull-up, pull-down, high Z, strong, or open drain drive modes on all GPIO Up to 14-bit ADCs Up to eight Analog Inputs on GPIO plus two additional analog Up to 8-bit DACs inputs with restricted routing Programmable gain amplifiers Two 30 mA analog outputs on GPIO Programmable filters and comparators Configurable interrupt on all GPIO Four digital PSoC blocks provide: Additional system resources 8- to 32-bit timers and counters, 8- and 16-bit pulse-width 2 I C slave, master, and multi-master to 400 kHz modulators (PWMs) Watchdog and sleep timers CRC and PRS modules User-configurable low voltage detection Full-duplex UART Integrated supervisory circuit Multiple SPI masters or slaves On-chip precision voltage reference Connectable to all GPIO Pins Complete development tools Complex peripherals by combining blocks Free development Software (PSoC Designer) High speed 8-bit SAR ADC optimized for motor control Full-featured In-Circuit Emulator and programmer Precision, programmable clocking Full speed emulation Internal 5% 24/48 MHz oscillator Complex breakpoint structure High accuracy 24 MHz with optional 32 kHz crystal and PLL 128KB trace memory Optional external oscillator, up to 24 MHz Internal oscillator for watchdog and sleep Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-20160 Rev. *H Revised September 15, 2014 CY8C24633 Block Diagram Analog Port 3 Port 2 Port 1 Port 0 Drivers PSoC CORE System Bus Global Digital Interconnect Global Analog Interconnect SRAM SROM Flash 8K 256 Bytes Sleep and CPU Core (M8C) Interrupt Watchdog Controller Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM ANALOG SYSTEM Analog Digital Analog Ref Block Block Array Array 2 Columns 4 Blocks 1 Row Analog 4 Blocks Input SAR8 ADC Muxing Internal Digital Multiply POR and LVD 2 Decimator I C Voltage Clocks Accum. System Resets Ref. SYSTEM RESOURCES Document Number: 001-20160 Rev. *H Page 2 of 52