Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY8C27143/CY8C27243 CY8C27443/CY8C27543 CY8C27643 PSoC Programmable System-on-Chip PSoC Programmable System-on-Chip Additional system resources Features 2 I C slave, master, and multi-master to 400 kHz Powerful Harvard-architecture processor Watchdog and sleep timers M8C processor speeds up to 24 MHz User-configurable low-voltage detection (LVD) 8 8 multiply, 32-bit accumulate Integrated supervisory circuit Low power at high speed On-chip precision voltage reference Operating voltage: 3.0 V to 5.25 V Complete development tools Operating voltages down to 1.0 V using on-chip switch mode Free development software (PSoC Designer) pump (SMP) Full-featured, in-circuit emulator (ICE) and programmer Industrial temperature range: 40 C to +85 C Full-speed emulation Advanced peripherals (PSoC blocks) Complex breakpoint structure Twelve rail-to-rail analog PSoC blocks provide: 128 KB trace memory Up to 14-bit analog-to-digital converters (ADCs) Up to 9-bit digital-to-analog converters (DACs) Logic Block Diagram Programmable gain amplifiers (PGAs) Programmable filters and comparators Analog Eight digital PSoC blocks provide: Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Drivers 8- to 32-bit timers and counters, 8- and 16-bit pulse-width PSoC modulators (PWMs) CORE Cyclical redundancy check (CRC) and pseudo random System Bus sequence (PRS) modules Up to two full-duplex universal asynchronous receiver transmitters (UARTs) Global Digital Interconnect Global Analog Interconnect Multiple serial peripheral interface (SPI)masters or slaves SRAM SROM Flash 16 KB Connectable to all general-purpose I/O (GPIO) pins 256 Bytes Complex peripherals by combining blocks Sleep and CPU Core (M8C) Interrupt Watchdog Controller Precision, programmable clocking Internal 2.5% 24- / 48-MHz main oscillator Multiple Clock Sources 24- / 48-MHz with optional 32 kHz crystal (Includes IMO, ILO, PLL, and ECO) Optional external oscillator up to 24 MHz Internal oscillator for watchdog and sleep DIGITAL SYSTEM ANALOG SYSTEM Flexible on-chip memory Analog Ref. 16 KB flash program storage 50,000 erase/write cycles Digital Analog 256-bytes SRAM data storage Block Block In-system serial programming (ISSP) Array Array Analog Partial flash updates Input Muxing Flexible protection modes Electronically erasable programmable read only memory (EEPROM) emulation in flash Programmable pin configurations POR and LVD Internal Switch 25-mA sink, 10-mA source on all GPIOs Digital Multiply 2 Decimator I C Voltage Mode Clocks Accum. Pull-up, pull-down, high-Z, strong, or open-drain drive modes System Resets Ref. Pump on all GPIOs SYSTEM RESOURCES Eight standard analog inputs on GPIO, plus four additional analog inputs with restricted routing Four 30-mA analog outputs on GPIOs Configurable interrupt on all GPIOs Errata: For information on silicon errata, see Errata on page 61. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-12012 Rev. AD Revised January 4, 2018