PSoC 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC ) General Description With its unique array of configurable blocks, PSoC 3 is a true ystem level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C32 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C32 family is also a high-performance configurable digital system with some 2 part numbers including interfaces such as USB, and multimaster inter-integrated circuit (I C). In addition to communication interfaces, the CY8C32 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator, a hierarchical schematic design entry tool. The CY8C32 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. Features 2 Single cycle 8051 CPU core Full-speed (FS) USB 2.0 12 Mbps using internal oscillator Up to four 16-bit configurable timer, counter, and PWM blocks DC to 50 MHz operation Library of standard peripherals Multiply and divide instructions 8-, 16-, 24-, and 32-bit timers, counters, and PWMs Flash program memory, up to 64 KB, 100,000 write cycles, Serial peripheral interface (SPI), universal asynchronous 20 years retention, and multiple security features 2 transmitter receiver (UART), and I C Up to 8-KB flash error correcting code (ECC) or configuration Many others available in catalog storage Library of advanced peripherals Up to 8 KB SRAM Cyclic redundancy check (CRC) Up to 2 KB electrically erasable programmable read-only Pseudo random sequence (PRS) generator memory (EEPROM), 1 M cycles, and 20 years retention Local interconnect network (LIN) bus 2.0 24-channel direct memory access (DMA) with multilayer 1 Quadrature decoder AHB bus access Programmable chained descriptors and priorities Analog peripherals (1.71 V V 5.5 V) DDA High bandwidth 32-bit transfer support 1.024 V 0.9-percent internal voltage reference across 40C to +85C (14 ppm/C) Low voltage, ultra low-power Configurable delta-sigma ADC with 8- to12-bit resolution Wide operating voltage range: 0.5 V to 5.5 V Programmable gain stage: 0.25 to 16 High efficiency boost regulator from 0.5-V through 1.8-V to 12-bit mode, 192-ksps, 66-dB signal to noise and distortion 5.0-V output ratio (SINAD), 1-bit INL/DNL 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz One 8-bit, 8-Msps IDAC or 1-Msps VDAC Low-power modes including: Two comparators with 95 ns response time 1-A sleep mode with real-time clock (RTC) and CapSense support low-voltage detect (LVD) interrupt 200-nA hibernate mode with RAM retention Programming, debug, and trace Versatile I/O system JTAG (4-wire), serial wire debug (SWD) (2-wire), and single wire viewer (SWV) interfaces 28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO), 2 Eight address and one data breakpoint two USBIOs ) 4-KB instruction trace buffer Any GPIO to any digital or analog peripheral routability 2 2 Bootloader programming supportable through I C, SPI, LCD direct drive from any GPIO, up to 4616 segments 3 UART, USB, and other interfaces CapSense support from any GPIO Precision, programmable clocking 1.2-V to 5.5-V I/O interface voltages, up to four domains 3- to 24-MHz internal oscillator over full temperature and Maskable, independent IRQ on any pin or port voltage range Schmitt-trigger transistor-transistor logic (TTL) inputs 4- to 25-MHz crystal oscillator for crystal PPM accuracy All GPIO configurable as open drain high/low, Internal PLL clock generation up to 50 MHz pull-up/pull-down, High Z, or strong output 32.768-kHz watch crystal oscillator Configurable GPIO pin state at power-on reset (POR) Low-power internal oscillator at 1, 33, and 100 kHz 25 mA sink on SIO Temperature and packaging Digital peripherals 40C to +85C degrees industrial temperature 16 to 24 programmable PLD based universal digital 48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP blocks (UDB) package options Notes 1. AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus 2. This feature on select devices only. See Ordering Information on page 108 for details. 3. GPIOs with opamp outputs are not recommended for use with CapSense. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-56955 Rev. *K Revised May 20, 2011 PSoC 3: CY8C32 Family Data Sheet Contents 1. Architectural Overview ..................................................... 3 8.5 CapSense ................................................................. 57 8.6 Temp Sensor ............................................................ 57 2. Pinouts ............................................................................... 5 8.7 DAC .......................................................................... 58 3. Pin Descriptions .............................................................. 10 9. Programming, Debug Interfaces, Resources ................ 59 4. CPU ................................................................................... 11 9.1 JTAG Interface ......................................................... 59 4.1 8051 CPU ................................................................. 11 9.2 Serial Wire Debug Interface ..................................... 61 4.2 Addressing Modes .................................................... 11 9.3 Debug Features ........................................................ 62 4.3 Instruction Set .......................................................... 12 9.4 Trace Features ......................................................... 62 4.4 DMA and PHUB ....................................................... 16 9.5 Single Wire Viewer Interface .................................... 62 4.5 Interrupt Controller ................................................... 18 9.6 Programming Features ............................................. 62 5. Memory ............................................................................. 22 9.7 Device Security ........................................................ 62 5.1 Static RAM ............................................................... 22 10. Development Support ................................................... 63 5.2 Flash Program Memory ............................................ 22 10.1 Documentation ....................................................... 63 5.3 Flash Security ........................................................... 22 10.2 Online ..................................................................... 63 5.4 EEPROM .................................................................. 22 10.3 Tools ....................................................................... 63 5.5 Nonvolatile Latches (NVLs) ...................................... 23 11. Electrical Specifications ............................................... 64 5.6 External Memory Interface ....................................... 24 11.1 Absolute Maximum Ratings .................................... 64 5.7 Memory Map ............................................................ 24 11.2 Device Level Specifications .................................... 65 6. System Integration .......................................................... 26 11.3 Power Regulators ................................................... 69 6.1 Clocking System ....................................................... 26 11.1 Inputs and Outputs ................................................. 73 6.2 Power System .......................................................... 29 11.2 Analog Peripherals ................................................. 81 6.3 Reset ........................................................................ 33 11.3 Digital Peripherals .................................................. 93 6.4 I/O System and Routing ........................................... 34 11.4 Memory .................................................................. 96 7. Digital Subsystem ........................................................... 40 11.5 PSoC System Resources ..................................... 102 7.1 Example Peripherals ................................................ 41 11.6 Clocking ................................................................ 104 7.2 Universal Digital Block .............................................. 44 12. Ordering Information ................................................... 108 7.3 UDB Array Description ............................................. 47 12.1 Part Numbering Conventions ............................... 109 7.4 DSI Routing Interface Description ............................ 47 13. Packaging ..................................................................... 110 7.5 USB .......................................................................... 49 7.6 Timers, Counters, and PWMs .................................. 49 14. Acronyms ..................................................................... 113 2 7.7 I C ............................................................................49 15. Reference Documents ................................................. 114 8. Analog Subsystem .......................................................... 51 16. Document Conventions .............................................. 115 8.1 Analog Routing ......................................................... 52 16.1 Units of Measure .................................................. 115 8.2 Delta-sigma ADC ...................................................... 54 17. Revision History .......................................................... 116 8.3 Comparators ............................................................. 55 18. Sales, Solutions, and Legal Information .................120 8.4 LCD Direct Drive ...................................................... 57 Document Number: 001-56955 Rev. *K Page 2 of 120