PSoC 3: CY8C36 Family Data Sheet Programmable System-on-Chip (PSoC ) General Description With its unique array of configurable blocks, PSoC 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C36 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C36 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C36 family is also a high-performance configurable digital system with some 2 part numbers including interfaces such as USB, multi-master inter-integrated circuit (I C), and controller area network (CAN). In addition to communication interfaces, the CY8C36 family has an easy to configure logic array, flexible routing to all I/O pins, and current DAC a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator, a hierarchical schematic design entry tool. The CY8C36 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. 67-MHz, 24-bit fixed point digital filter block (DFB) to Features implement finite impulse response (FIR) and infinite impulse Single cycle 8051 CPU core response (IIR) filters DC to 67 MHz operation Library of standard peripherals Multiply and divide instructions 8-, 16-, 24-, and 32-bit timers, counters, and PWMs Flash program memory, up to 64 KB, 100,000 write cycles, Serial peripheral interface (SPI), universal asynchronous 20 years retention, and multiple security features 2 transmitter receiver (UART), I C Up to 8-KB flash error correcting code (ECC) or configuration Many others available in catalog storage Library of advanced peripherals Up to 8 KB SRAM Cyclic redundancy check (CRC) Up to 2 KB electrically erasable programmable Pseudo random sequence (PRS) generator read-only memory (EEPROM), 1 M cycles, and 20 years Local interconnect network (LIN) bus 2.0 retention Quadrature decoder 24-channel direct memory access (DMA) with multilayer 1 Analog peripherals (1.71 V V 5.5 V) DDA AHB bus access 1.024 V 0.1% internal voltage reference across 40 C to Programmable chained descriptors and priorities +85 C (14 ppm/C) High bandwidth 32-bit transfer support Configurable delta-sigma ADC with 8- to12-bit resolution Low voltage, ultra low-power Programmable gain stage: 0.25 to 16 Wide operating voltage range: 0.5 V to 5.5 V 12-bit mode, 192-ksps, 66-dB signal to noise and distortion High efficiency boost regulator from 0.5-V input through ratio (SINAD), 1-bit INL/DNL 1.8-V to 5.0-V output Up to four 8-bit, 8-Msps IDACs or 1-Msps VDACs 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, 6.6 mA at 48 MHz Four comparators with 95-ns response time Low-power modes including: Up to four uncommitted opamps with 25 mA drive capability 1-A sleep mode with real-time clock (RTC) and Up to four configurable multifunction analog blocks. Example low-voltage detect (LVD) interrupt configurations are programmable gain amplifier (PGA), 200-nA hibernate mode with RAM retention transimpedance amplifier (TIA), mixer, and sample and hold Versatile I/O system CapSense support 28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO), two Programming, debug, and trace 2 USBIOs JTAG (4-wire), serial wire debug (SWD) (2-wire), and single Any GPIO to any digital or analog peripheral routability wire viewer (SWV) interfaces 2 LCD direct drive from any GPIO, up to 46 16 segments Eight address and one data breakpoint 3 CapSense support from any GPIO 4-KB instruction trace buffer 1.2-V to 5.5-V I/O interface voltages, up to four domains 2 Bootloader programming supportable through I C, SPI, Maskable, independent interrupt request (IRQ) on any pin or UART, USB, and other interfaces port Precision, programmable clocking Schmitt-trigger transistor-transistor logic (TTL) inputs 3- to 62-MHz internal oscillator over full temperature and All GPIO configurable as open drain high/low, voltage range pull-up/pull-down, High Z, or strong output 4- to 25-MHz crystal oscillator for crystal PPM accuracy Configurable GPIO pin state at power-on reset (POR) Internal PLL clock generation up to 67 MHz 25 mA sink on SIO 32.768 kHz watch crystal oscillator Digital peripherals Low-power internal oscillator at 1, 33, and 100 kHz 20 to 24 programmable logic devices (PLD) based universal Temperature and packaging digital blocks (UDB) 40 C to +85 C degrees industrial temperature 2 Full CAN 2.0b 16-receive (Rx), 8-transmit (Tx) buffers 2 48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator package options Up to four 16-bit configurable timer, counter, and PWM blocks Notes 1. AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus 2. This feature on select devices only. See Ordering Information on page 114 for details. 3. GPIOs with opamp outputs are not recommended for use with CapSense. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-53413 Rev. *L Revised May 20, 2011 PSoC 3: CY8C36 Family Data Sheet Contents 1. Architectural Overview ..................................................... 3 8.6 LCD Direct Drive ...................................................... 56 8.7 CapSense ................................................................. 57 2. Pinouts ............................................................................... 5 8.8 Temp Sensor ............................................................ 57 3. Pin Descriptions .............................................................. 10 8.9 DAC .......................................................................... 57 4. CPU ................................................................................... 11 8.10 Up/Down Mixer ....................................................... 58 4.1 8051 CPU ................................................................. 11 8.11 Sample and Hold .................................................... 58 4.2 Addressing Modes .................................................... 11 9. Programming, Debug Interfaces, Resources ................ 59 4.3 Instruction Set .......................................................... 11 9.1 JTAG Interface ......................................................... 59 4.4 DMA and PHUB ....................................................... 15 9.2 Serial Wire Debug Interface ..................................... 61 4.5 Interrupt Controller ................................................... 17 9.3 Debug Features ........................................................ 62 5. Memory ............................................................................. 20 9.4 Trace Features ......................................................... 62 5.1 Static RAM ............................................................... 20 9.5 Single Wire Viewer Interface .................................... 62 5.2 Flash Program Memory ............................................ 20 9.6 Programming Features ............................................. 62 5.3 Flash Security ........................................................... 20 9.7 Device Security ........................................................ 62 5.4 EEPROM .................................................................. 21 10. Development Support ................................................... 63 5.5 Nonvolatile Latches (NVLs) ...................................... 21 10.1 Documentation ....................................................... 63 5.6 External Memory Interface ....................................... 22 10.2 Online ..................................................................... 63 5.7 Memory Map ............................................................ 22 10.3 Tools ....................................................................... 63 6. System Integration .......................................................... 25 11. Electrical Specifications ............................................... 64 6.1 Clocking System ....................................................... 25 11.1 Absolute Maximum Ratings .................................... 64 6.2 Power System .......................................................... 28 11.2 Device Level Specifications .................................... 65 6.3 Reset ........................................................................ 31 11.3 Power Regulators ................................................... 69 6.4 I/O System and Routing ........................................... 32 11.4 Inputs and Outputs ................................................. 73 7. Digital Subsystem ........................................................... 38 11.5 Analog Peripherals ................................................. 80 7.1 Example Peripherals ................................................ 39 11.6 Digital Peripherals .................................................. 97 7.2 Universal Digital Block .............................................. 42 11.7 Memory ................................................................ 101 7.3 UDB Array Description ............................................. 45 11.8 PSoC System Resources ..................................... 107 7.4 DSI Routing Interface Description ............................ 45 11.9 Clocking ................................................................ 110 7.5 CAN .......................................................................... 47 12. Ordering Information ................................................... 114 7.6 USB .......................................................................... 48 12.1 Part Numbering Conventions ............................... 115 7.7 Timers, Counters, and PWMs .................................. 49 2 13. Packaging ..................................................................... 116 7.8 I C ............................................................................49 7.9 Digital Filter Block ..................................................... 50 14. Acronyms ..................................................................... 119 8. Analog Subsystem .......................................................... 50 15. Reference Documents ................................................. 120 8.1 Analog Routing ......................................................... 51 16. Document Conventions .............................................. 121 8.2 Delta-sigma ADC ...................................................... 53 16.1 Units of Measure .................................................. 121 8.3 Comparators ............................................................. 54 17. Revision History .......................................................... 122 8.4 Opamps .................................................................... 55 18. Sales, Solutions, and Legal Information ................... 126 8.5 Programmable SC/CT Blocks .................................. 55 Document Number: 001-53413 Rev. *L Page 2 of 126