Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com PSoC 4: PSoC 4000 Family Datasheet Programmable System-on-Chip (PSoC ) General Description PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm Cortex-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4000 product family is the smallest member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, and general-purpose analog. PSoC 4000 products will be fully upward compatible with members of the PSoC 4 platform for new applica- tions and design needs. Features 32-bit MCU Subsystem Timing and Pulse-Width Modulation 16-MHz Arm Cortex-M0 CPU One 16-bit timer/counter/pulse-width modulator (TCPWM) block Up to 16 KB of flash with Read Accelerator Up to 2 KB of SRAM Center-aligned, Edge, and Pseudo-Random modes Comparator-based triggering of Kill signals for motor drive and Programmable Analog other high-reliability digital logic applications Two current DACs (IDACs) for general-purpose or capacitive sensing applications Up to 20 Programmable GPIO Pins One low-power comparator with internal reference 28-pin SSOP, 24-pin QFN, 16-pin SOIC, 16-pin QFN, 16 ball Limited ADC function provided by capacitance sensing block WLCSP, and 8-pin SOIC packages GPIO pins on Ports 0, 1, and 2 can be CapSense or have other Low Power 1.71-V to 5.5-V operation functions 2 Deep Sleep mode with wake-up on interrupt and I C address Drive modes, strengths, and slew rates are programmable detect PSoC Creator Design Environment Capacitive Sensing Integrated Development Environment (IDE) provides Cypress CapSense Sigma-Delta (CSD) provides best-in-class schematic design entry and build (with analog and digital signal-to-noise ratio (SNR) and water tolerance automatic routing) Cypress-supplied software component makes capacitive Applications Programming Interface (API) component for all sensing design easy fixed-function and programmable peripherals Automatic hardware tuning (SmartSense) over a sensor range of 5 pF to 45 pF Industry-Standard Tool Compatibility After schematic entry, development can be done with Serial Communication Arm-based industry-standard development tools 2 Multi-master I C block with the ability to do address matching during Deep Sleep and generate a wake-up on match Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-89638 Rev. *K Revised March 15, 2021