Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com PSoC 4: PSoC 4100 Family Datasheet Programmable System-on-Chip (PSoC ) General Description PSoC 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system controllers with an Arm Cortex-M0 CPU. It combinesArm programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4100 product family, based on this platform, is a combination of a microcontroller with digital program- mable logic, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing peripherals. The PSoC 4100 products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital sub-systems allow flexibility and in-field tuning of the design. Features 32-bit MCU Sub-system Timing and Pulse-Width Modulation 24-MHz Arm Cortex-M0 CPU with single-cycle multiply Four 16-bit timer/counter pulse-width modulator (TCPWM) blocks Up to 32 kB of flash with Read Accelerator Up to 4 kB of SRAM Center-aligned, Edge, and Pseudo-random modes Comparator-based triggering of Kill signals for motor drive and Programmable Analog other high reliability digital logic applications Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC Up to 36 Programmable GPIOs input buffering capability Any GPIO pin can be CapSense, LCD, analog, or digital 12-bit 806 ksps SAR ADC with differential and single-ended modes and Channel Sequencer with signal averaging Drive modes, strengths, and slew rates are programmable Two current DACs (IDACs) for general-purpose or capacitive Five different packages sensing applications on any pin 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 35-ball WLCSP, and Two low-power comparators that operate in Deep Sleep 28-pin SSOP package Low Power 1.71-V to 5.5-V operation 2 35-ball WLCSP package is shipped with I C Bootloader in Flash 20-nA Stop Mode with GPIO pin wakeup Hibernate and Deep Sleep modes allow wakeup-time versus Extended Industrial Temperature Operation power trade-offs 40 C to + 105 C operation Capacitive Sensing PSoC Creator Design Environment Cypress CapSense Sigma-Delta (CSD) provides best-in-class Integrated Development Environment provides schematic SNR (>5:1) and water tolerance design entry and build (with analog and digital automatic Cypress supplied software component makes capacitive routing) sensing design easy Applications Programming Interface (API Component) for all Automatic hardware tuning (SmartSense) fixed-function and programmable peripherals Segment LCD Drive Industry Standard Tool Compatibility LCD drive supported on all pins (common or segment) After schematic entry, development can be done with Arm-based industry-standard development tools Operates in Deep Sleep mode with 4 bits per pin memory Serial Communication Two independent run-time reconfigurable serial communi- 2 cation blocks (SCBs) with reconfigurable I C, SPI, or UART functionality Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-87220 Rev. *K Revised July 2, 2019