PSoC 4: PSoC 4XX7 BLE Family Datasheet Programmable System-on-Chip (PSoC ) General Description PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an ARM Cortex -M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4XX7 BLE product family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth Low Energy (BLE), also known as Bluetooth Smart, radio and subsystem (BLESS). The other features include digital programmable logic, high-performance analog-to-digital conversion (ADC), opamps with comparator mode, and standard communication and timing peripherals. The PSoC 4XX7 BLE products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design. Features 32-bit MCU Subsystem Capacitive Sensing 48-MHz ARM Cortex-M0 CPU with single-cycle multiply Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance Up to 128 KB of flash with Read Accelerator Cypress-supplied software component makes Up to 16 KB of SRAM capacitive-sensing design easy BLE Radio and Subsystem Automatic hardware-tuning algorithm (SmartSense) 2.4-GHz RF transceiver with 50- antenna drive Segment LCD Drive Digital PHY LCD drive supported on all pins (common or segment) Link Layer engine supporting master and slave modes Operates in Deep-Sleep mode with four bits per pin memory RF output power: 18 dBm to +3 dBm Serial Communication RX sensitivity: 89 dBm Two independent runtime reconfigurable serial communication RX current: 16.4 mA 2 blocks (SCBs) with reconfigurable I C, SPI, or UART function- TX current: 15.6 mA at 0 dBm ality Received Signal Strength Indication (RSSI): 1-dB resolution Timing and Pulse-Width Modulation Programmable Analog Four 16-bit timer, counter, pulse-width modulator (TCPWM) blocks Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, comparator modes, and ADC Center-aligned, Edge, and Pseudo-random modes input buffering capability can operate in Deep-Sleep mode. Comparator-based triggering of Kill signals for motor drive and 12-bit, 1-Msps SAR ADC with differential and single-ended other high-reliability digital logic applications modes channel sequencer with signal averaging Up to 36 Programmable GPIOs Two current DACs (IDACs) for general-purpose or capacitive 7mm 7mm 56-pin QFN package sensing applications on any pin 3.51 mm 3.91 mm 68-ball CSP package Two low-power comparators that operate in Deep-Sleep mode Any GPIO pin can be CapSense, LCD, analog, or digital Programmable Digital Two overvoltage-tolerant (OVT) pins drive modes, strengths, Four programmable logic blocks called universal digital blocks, and slew rates are programmable (UDBs), each with eight macrocells and datapath PSoC Creator Design Environment Cypress-provided peripheral Component library, user-defined state machines, and Verilog input Integrated design environment (IDE) provides schematic design entry and build (with analog and digital automatic Power Management routing) Active mode: 1.7 mA at 3-MHz flash program execution API components for all fixed-function and programmable Deep-Sleep mode: 1.3 A with watch crystal oscillator (WCO) peripherals on Industry-Standard Tool Compatibility Hibernate mode: 150 nA with RAM retention After schematic entry, development can be done with Stop mode: 60 nA ARM-based industry-standard development tools Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-90479 Rev. *N Revised April 24, 2017 PSoC 4: PSoC 4XX7 BLE Family Datasheet More Information Cypress provides a wealth of data at