Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com PSoC 4: PSoC 4100 BLE Family Datasheet Programmable System-on-Chip (PSoC ) General Description PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm Cortex -M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4100 BLE product family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth Low Energy (BLE), also known as Bluetooth Smart, radio and subsystem (BLESS), compliant with Bluetooth 4.2 specifications. The other features include digital programmable logic, high-performance analog-to-digital conversion (ADC), opamps with comparator mode, and standard communication and timing peripherals. The PSoC 4100 BLE products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design. Features 32-bit MCU Subsystem Segment LCD Drive 24-MHz Arm Cortex-M0 CPU with single-cycle multiply LCD drive supported on all pins (common or segment) Up to 256 KB of flash with Read Accelerator Operates in Deep-Sleep mode with four bits per pin memory Up to 32 KB of SRAM Serial Communication BLE Radio and Subsystem Two independent runtime reconfigurable serial communication 2 blocks (SCBs) with reconfigurable I C, SPI, or UART function- 2.4-GHz RF transceiver with BLE 4.2 support and 50- ality antenna drive Timing and Pulse-Width Modulation Digital PHY Four 16-bit timer, counter, pulse-width modulator (TCPWM) Link Layer engine supporting master and slave modes blocks RF output power: 18 dBm to +3 dBm Center-aligned, Edge, and Pseudo-random modes RX sensitivity: 89 dBm Comparator-based triggering of Kill signals for motor drive and RX current: 16.4 mA other high-reliability digital logic applications TX current: 15.6 mA at 0 dBm Up to 36 Programmable GPIOs Received Signal Strength Indication (RSSI): 1-dB resolution 7mm 7mm 56-pin QFN package Programmable Analog 3.51 mm 3.91 mm 68-ball CSP package Two opamps with reconfigurable high-drive external and Any GPIO pin can be CapSense, LCD, analog, or digital high-bandwidth internal drive, comparator modes, and ADC Two overvoltage-tolerant (OVT) pins drive modes, strengths, input buffering capability can operate in Deep-Sleep mode. and slew rates are programmable 12-bit, 806 ksps SAR ADC with differential and single-ended modes channel sequencer with signal averaging PSoC Creator Design Environment Two current DACs (IDACs) for general-purpose or capacitive Integrated design environment (IDE) provides schematic sensing applications on any pin design entry and build (with analog and digital automatic routing) Two low-power comparators that operate in Deep-Sleep mode API components for all fixed-function and programmable Power Management peripherals Active mode: 1.7 mA at 3-MHz flash program execution Industry-Standard Tool Compatibility Deep-Sleep mode: 1.3 A with watch crystal oscillator (WCO) After schematic entry, development can be done with on Arm-based industry-standard development tools Hibernate mode: 150 nA with RAM retention Stop mode: 60 nA Capacitive Sensing Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance Cypress-supplied software component makes capacitive-sensing design easy Automatic hardware-tuning algorithm (SmartSense) Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-23052 Rev. ** Revised February 22, 2018