Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comPSoC 4: PSoC 4200DS Family Datasheet Programmable System-on-Chip (PSoC) General Description PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm Cortex -M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4200DS product family, based on this platform architecture, is a combination of a microcontroller with digital programmable logic, programmable interconnect, and standard communication and timing peripherals. The PSoC 4200DS products will be fully compatible with members of the PSoC 4 platform for new applications and design needs. The programmable digital subsystem allows flexibility and in-field tuning of the design. Features 32-bit MCU Subsystem Packages 48 MHz Arm Cortex-M0 CPU with single-cycle multiply 25-ball CSP package 2.07 mm 2.11 mm, 28-pin SSOP package. Up to 64 kB of flash with Read Accelerator Up to 8 kB of SRAM Up to 21 programmable GPIOs DMA engine GPIO drive modes, strengths, and slew rates are program- mable Programmable Digital PSoC Creator Design Environment Four programmable logic blocks, each with 8 Macrocells and an 8-bit data path (called universal digital blocks or UDBs) Integrated development environment (IDE) provides schematic design entry and build (with analog and digital automatic Programmable I/O block (PRGIO) provides the ability to routing) perform Boolean functions in the I/O signal path Cypress-provided peripheral component library, user-defined Application programming interface (API) component for all state machines, and Verilog input fixed-function and programmable peripherals Low Power 1.71 to 5.5 V Operation Industry-Standard Tool Compatibility Low-power Deep Sleep Mode with GPIO pin wakeup After schematic entry, development can be done with Arm-based industry-standard development tools Serial Communication Three independent run-time reconfigurable serial 2 communication blocks (SCBs) with reconfigurable I C, SPI, or UART functionality Timing and Pulse-Width Modulation Four 16-bit timer/counter pulse-width modulator (TCPWM) blocks Center-aligned, Edge, and Pseudo-random modes Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-98044 Rev. *E Revised December 17, 2020