Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com PSoC 4: 4200 BLE Family Datasheet Programmable System-on-Chip (PSoC ) General Description PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm Cortex -M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4200 BL product family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth Low Energy (BLE), also known as Bluetooth Smart, radio and subsystem (BLESS). The other features include digital programmable logic, high-performance analog-to-digital conversion (ADC), opamps with Comparator mode, and standard communication and timing peripherals. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design. Features 32-bit MCU Subsystem Capacitive Sensing 48-MHz Arm Cortex-M0 CPU with single-cycle multiply and Cypress Capacitive Sigma-Delta (CSD) provides best-in-class DMA SNR (>5:1) and liquid tolerance Up to 256 KB of flash with Read Accelerator Cypress-supplied software component makes capacitive sensing design easy Up to 32 KB of SRAM Automatic hardware tuning algorithm (SmartSense) BLE Radio and Subsystem Segment LCD Drive BLE 4.2 support LCD drive supported on all pins (common or segment) 2.4-GHz RF transceiver with 50- antenna drive Operates in Deep Sleep mode with four bits per pin memory Digital PHY Serial Communication Link-Layer engine supporting master and slave modes Two independent run-time reconfigurable serial communi- RF output power: 18 dBm to +3 dBm 2 cation blocks (SCBs) with reconfigurable I C, SPI, or UART RX sensitivity: 89 dBm functionality RX current: 18.7 mA Timing and Pulse-Width Modulation TX current: 15.6 mA at 0 dBm Four 16-bit timer/counter pulse-width modulator (TCPWM) RSSI: 1-dB resolution blocks Programmable Analog Center-aligned, Edge, and Pseudo-random modes Four opamps with reconfigurable high-drive external and Comparator-based triggering of Kill signals for motor drive and high-bandwidth internal drive, Comparator modes, and ADC other high-reliability digital logic applications input buffering capability. Can operate in Deep Sleep mode. Up to 36 Programmable GPIOs 12-bit, 1-Msps SAR ADC with differential and single-ended 7mm 7mm 56-pin QFN package modes Channel Sequencer with signal averaging 76-ball CSP package Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin 68-ball CSP package Two low-power comparators that operate in Deep Sleep mode Any GPIO pin can be CapSense, LCD, analog, or digital Two overvoltage-tolerant (OVT) pins drive modes, strengths, Programmable Digital and slew rates are programmable Four programmable logic blocks called universal digital blocks, (UDBs), each with eight macrocells and data path PSoC Creator Design Environment Cypress-provided peripheral component library, user-defined Integrated Design Environment (IDE) provides schematic state machines, and Verilog input design entry and build (with analog and digital automatic routing) Power Management API components for all fixed-function and programmable Active mode: 1.7 mA at 3-MHz flash program execution peripherals Deep Sleep mode: 1.5 A with watch crystal oscillator (WCO) on Industry-Standard Tool Compatibility Hibernate mode: 150 nA with RAM retention After schematic entry, development can be done with Arm-based industry-standard development tools Stop mode: 60 nA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-23053 Rev. ** Revised February 22, 2018