Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com PSoC 5LP: CY8C52LP Family Datasheet Programmable System-on-Chip (PSoC ) General Description PSoC 5LP is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a microcontroller on a single chip. The PSoC 5LP architecture boosts performance through: 32-bit Arm Cortex -M3 core plus DMA controller at up to 80 MHz Ultra low power with industrys widest voltage range Programmable digital and analog peripherals enable custom functions Flexible routing of any analog or digital peripheral function to any pin PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality. Features Operating characteristics Analog peripherals Voltage range: 1.71 to 5.5 V, up to 6 power domains 12-bit SAR ADC 1 Temperature range (ambient) 40 to 85 C 8-bit DAC DC to 80-MHz operation Two comparators Power modes CapSense support, up to 62 sensors Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz 1.024 V 1% internal voltage reference 2-A sleep mode Versatile I/O system 300-nA hibernate mode with RAM retention 46 to 72 I/O pins up to 62 general-purpose I/Os (GPIOs) Boost regulator from 0.5-V input up to 5-V output Up to eight performance I/O (SIO) pins Performance 25 mA current sink 32-bit Arm Cortex-M3 CPU, 32 interrupt inputs Programmable input threshold and output high voltages Can act as a general-purpose comparator 24-channel direct memory access (DMA) controller Hot swap capability and overvoltage tolerance Memories Two USBIO pins that can be used as GPIOs Up to 256 KB program flash, with cache and security features Route any digital or analog peripheral to any GPIO Up to 32 KB additional flash for error correcting code (ECC) LCD direct drive from any GPIO, up to 46 16 segments Up to 64 KB RAM CapSense support from any GPIO 2 KB EEPROM 1.2-V to 5.5-V interface voltages, up to four power domains Digital peripherals Programming, debug, and trace Four 16-bit timer, counter, and PWM (TCPWM) blocks JTAG (4-wire), serial wire debug (SWD) (2-wire), single wire 2 I C, 1 Mbps bus speed viewer (SWV), and Traceport (5-wire) interfaces USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral inter- Arm debug and trace modules embedded in the CPU core 2 face (TID 10840032) using internal oscillator 2 Bootloader programming through I C, SPI, UART, USB, and 20 to 24 universal digital blocks (UDB), programmable to other interfaces create any number of functions: 8-, 16-, 24-, and 32-bit timers, counters, and PWMs Package options: 68-pin QFN,100-pin TQFP, and 99-pin CSP 2 I C, UART, SPI, I2S, LIN 2.0 interfaces Development support with free PSoC Creator tool Cyclic redundancy check (CRC) Schematic and firmware design support Pseudo random sequence (PRS) generators Over 100 PSoC Components integrate multiple ICs and Quadrature decoders system interfaces into one PSoC. Components are free Gate-level logic functions embedded ICs represented by icons. Drag and drop Programmable clocking component icons to design systems in PSoC Creator. 3- to 74-MHz internal oscillator, 2% accuracy at 3 MHz Includes free GCC compiler, supports Keil/Arm MDK 4- to 25-MHz external crystal oscillator compiler Internal PLL clock generation up to 80 MHz Supports device programming and debugging Low-power internal oscillator at 1, 33, and 100 kHz 32.768-kHz external watch crystal oscillator 12 clock dividers routable to any peripheral or I/O Notes 1. The maximum storage temperature is 150 C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. This feature on select devices only. See Ordering Information on page 104 for details. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-84933 Rev. *N Revised November 27, 2019