PSoC 5LP: CY8C58LP Family PRELIMINARY Datasheet Programmable System-on-Chip (PSoC ) General Description With its unique array of configurable blocks, PSoC 5LP is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C58LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C58LP family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C58LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN). In addition to communication interfaces, the CY8C58LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM Cortex-M3 microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator, a hierarchical schematic design entry tool. The CY8C58LP family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. Library of advanced peripherals Features Cyclic redundancy check (CRC) 32-bit ARM Cortex-M3 CPU core Pseudo random sequence (PRS) generator DC to 67 MHz operation Local interconnect network (LIN) bus 2.0 Flash program memory, up to 256 KB, 100,000 write cycles, Quadrature decoder 20-year retention, and multiple security features Up to 32-KB flash error correcting code (ECC) or configura- Analog peripherals (1.71 V V 5.5 V) DDA tion storage 1.024 V 0.1% internal voltage reference across 40C to Up to 64 KB SRAM +85C Configurable delta-sigma ADC with 8- to 20-bit resolution 2-KB electrically erasable programmable read-only memory (EEPROM) memory, 1 M cycles, and 20 years retention Sample rates up to 192 ksps 24-channel direct memory access (DMA) with multilayer Programmable gain stage: 0.25 to 16 1 AHB bus access 12-bit mode, 192 ksps, 66-dB signal to noise and distortion Programmable chained descriptors and priorities ratio (SINAD), 1-bit INL/DNL High bandwidth 32-bit transfer support 16-bit mode, 48 ksps, 84-dB SINAD, 2-bit INL, 1-bit DNL Low voltage, ultra low power Up to two SAR ADCs, each 12-bit at 1 Msps Wide operating voltage range: 0.5 V to 5.5 V Four 8-bit 8 Msps current IDACs or 1-Msps voltage VDACs High-efficiency boost regulator from 0.5 V input to 1.8 V to Four comparators with 95-ns response time 5.0 V output Four uncommitted opamps with 25-mA drive capability 3.1 mA at 6 MHz Four configurable multifunction analog blocks. Example con- Low power modes including: figurations are programmable gain amplifier (PGA), tran- simpedance amplifier (TIA), mixer, and sample and hold 2-A sleep mode with real time clock (RTC) and low-volt- age detect (LVD) interrupt CapSense support 300-nA hibernate mode with RAM retention Programming, debug, and trace Versatile I/O system JTAG (4 wire), serial wire debug (SWD) (2 wire), single wire 2 viewer (SWV), and TRACEPORT interfaces 28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs ) Cortex-M3 flash patch and breakpoint (FPB) block Any GPIO to any digital or analog peripheral routability Cortex-M3 Embedded Trace Macrocell (ETM) gener- LCD direct drive from any GPIO, up to 4616 segments 3 ates an instruction trace stream. CapSense support from any GPIO Cortex-M3 data watchpoint and trace (DWT) generates data 1.2 V to 5.5 V I/O interface voltages, up to 4 domains trace information Maskable, independent IRQ on any pin or port Cortex-M3 Instrumentation Trace Macrocell (ITM) can be Schmitt-trigger transistor-transistor logic (TTL) inputs used for printf-style debugging All GPIOs configurable as open drain high/low, DWT, ETM, and ITM blocks communicate with off-chip debug pull-up/pull-down, High-Z, or strong output and trace systems via the SWV or TRACEPORT 2 Configurable GPIO pin state at power-on reset (POR) Bootloader programming supportable through I C, SPI, 25 mA sink on SIO UART, USB, and other interfaces Digital peripherals Precision, programmable clocking 20 to 24 programmable logic device (PLD) based universal 3- to 62-MHz internal oscillator over full temperature and volt- digital blocks (UDBs) age range 2 Full CAN 2.0b 16 RX, 8 TX buffers 4- to 25-MHz crystal oscillator for crystal PPM accuracy 2 Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator Internal PLL clock generation up to 67 MHz Four 16-bit configurable timers, counters, and PWM blocks 32.768-kHz watch crystal oscillator 67-MHz, 24-bit fixed point digital filter block (DFB) to Low power internal oscillator at 1, 33, and 100 kHz implement finite impulse response (FIR) and infinite impulse Temperature and packaging response (IIR) filters 40 C to +85 C degrees industrial temperature Library of standard peripherals 68-pin QFN and 100-pin TQFP package options. 8-, 16-, 24-, and 32-bit timers, counters, and PWMs Serial peripheral interface (SPI), universal asynchronous 2 transmitter receiver (UART), and I C Many others available in catalog Notes 1. AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus 2. This feature on select devices only. See Ordering Information on page 115 for details. 3. GPIOs with opamp outputs are not recommended for use with CapSense. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-84932 Rev. ** Revised December 7, 2012 PSoC 5LP: CY8C58LP Family PRELIMINARY Datasheet Contents 1. Architectural Overview ................................................. 3 8.7 LCD Direct Drive ..................................................54 8.8 CapSense .............................................................55 2. Pinouts ........................................................................... 5 8.9 Temp Sensor ........................................................55 3. Pin Descriptions ............................................................ 9 8.10 DAC ....................................................................55 4. CPU ............................................................................... 11 8.11 Up/Down Mixer ...................................................56 4.1 ARM Cortex-M3 CPU ...........................................11 8.12 Sample and Hold ................................................56 4.2 Cache Controller ..................................................12 9. Programming, Debug Interfaces, Resources ............ 57 4.3 DMA and PHUB ...................................................12 9.1 JTAG Interface .....................................................57 4.4 Interrupt Controller ...............................................15 9.2 SWD Interface ......................................................59 5. Memory ......................................................................... 17 9.3 Debug Features ....................................................60 5.1 Static RAM ...........................................................17 9.4 Trace Features .....................................................60 5.2 Flash Program Memory ........................................17 9.5 SWV and TRACEPORT Interfaces ......................60 5.3 Flash Security .......................................................17 9.6 Programming Features .........................................60 5.4 EEPROM ..............................................................17 9.7 Device Security ....................................................60 5.5 Nonvolatile Latches (NVLs) ..................................18 10. Development Support ............................................... 61 5.6 External Memory Interface ...................................19 10.1 Documentation ...................................................61 5.7 Memory Map ........................................................20 10.2 Online .................................................................61 6. System Integration ...................................................... 21 10.3 Tools ...................................................................61 6.1 Clocking System ...................................................21 11. Electrical Specifications ........................................... 62 6.2 Power System ......................................................24 11.1 Absolute Maximum Ratings ................................62 6.3 Reset ....................................................................28 11.2 Device Level Specifications ................................63 6.4 I/O System and Routing .......................................29 11.3 Power Regulators ...............................................65 7. Digital Subsystem ....................................................... 36 11.4 Inputs and Outputs .............................................69 7.1 Example Peripherals ............................................36 11.5 Analog Peripherals .............................................77 7.2 Universal Digital Block ..........................................38 11.6 Digital Peripherals ............................................100 7.3 UDB Array Description .........................................41 11.7 Memory ............................................................104 7.4 DSI Routing Interface Description ........................41 11.8 PSoC System Resources .................................108 7.5 CAN ......................................................................43 11.9 Clocking ............................................................111 7.6 USB ......................................................................44 12. Ordering Information ............................................... 115 7.7 Timers, Counters, and PWMs ..............................44 12.1 Part Numbering Conventions ...........................116 2 7.8 I C ........................................................................45 13. Packaging ................................................................. 117 7.9 Digital Filter Block .................................................46 14. Acronyms ................................................................. 119 8. Analog Subsystem ...................................................... 46 8.1 Analog Routing .....................................................48 15. Reference Documents ............................................. 120 8.2 Delta-sigma ADC ..................................................50 16. Document Conventions .......................................... 121 8.3 Successive Approximation ADC ...........................51 16.1 Units of Measure ..............................................121 8.4 Comparators .........................................................51 17. Revision History ...................................................... 122 8.5 Opamps ................................................................53 18. Sales, Solutions, and Legal Information ............... 122 8.6 Programmable SC/CT Blocks ..............................53 Document Number: 001-84932 Rev. ** Page 2 of 122