Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com PSoC 5LP: CY8C58LP Family Datasheet Programmable System-on-Chip (PSoC ) General Description PSoC 5LP is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a microcontroller on a single chip. The PSoC 5LP architecture boosts performance through: 32-bit Arm Cortex-M3 core plus DMA controller and digital filter processor, at up to 80 MHz Ultra low power with industry s widest voltage range Programmable digital and analog peripherals enable custom functions Flexible routing of any analog or digital peripheral function to any pin PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality. Features Operating characteristics Analog peripherals Voltage range: 1.71 to 5.5 V, up to 6 power domains Configurable 8- to 20-bit delta-sigma ADC 1 Up to two 12-bit SAR ADCs Temperature range (ambient): 40 to 85 C Extended temperature parts: 40 to 105 C Four 8-bit DACs DC to 80-MHz operation Four comparators Power modes Four opamps Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz Four programmable analog blocks, to create: 2-A sleep mode Programmable gain amplifier (PGA) 300-nA hibernate mode with RAM retention Transimpedance amplifier (TIA) Mixer Boost regulator from 0.5-V input up to 5-V output Sample and hold circuit Performance CapSense support, up to 62 sensors 32-bit Arm Cortex-M3 CPU, 32 interrupt inputs 1.024 V 0.1% internal voltage reference 24-channel direct memory access (DMA) controller 24-bit 64-tap fixed-point digital filter processor (DFB) Versatile I/O system Memories 46 to 72 I/O pins up to 62 general-purpose I/Os (GPIOs) Up to eight performance I/O (SIO) pins Up to 256 KB program flash, with cache and security features Up to 32 KB additional flash for error correcting code (ECC) 25 mA current sink Up to 64 KB RAM Programmable input threshold and output high voltages 2 KB EEPROM Can act as a general-purpose comparator Digital peripherals Hot swap capability and overvoltage tolerance Two USBIO pins that can be used as GPIOs Four 16-bit timer, counter, and PWM (TCPWM) blocks 2 I C, 1 Mbps bus speed Route any digital or analog peripheral to any GPIO USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral inter- LCD direct drive from any GPIO, up to 46 16 segments 2 face (TID 10840032) using internal oscillator CapSense support from any GPIO Full CAN 2.0b, 16 Rx, 8 Tx buffers 1.2-V to 5.5-V interface voltages, up to four power domains 20 to 24 universal digital blocks (UDB), programmable to Programming, debug, and trace create any number of functions: 8-, 16-, 24-, and 32-bit timers, counters, and PWMs JTAG (4-wire), serial wire debug (SWD) (2-wire), single wire 2 I C, UART, SPI, I2S, LIN 2.0 interfaces viewer (SWV), and Traceport (5-wire) interfaces Arm debug and trace modules embedded in the CPU core Cyclic redundancy check (CRC) 2 Bootloader programming through I C, SPI, UART, USB, and Pseudo random sequence (PRS) generators other interfaces Quadrature decoders Package options: 68-pin QFN, 100-pin TQFP, and 99-pin CSP Gate-level logic functions Development support with free PSoC Creator tool Programmable clocking Schematic and firmware design support 3- to 74-MHz internal oscillator, 1% accuracy at 3 MHz Over 100 PSoC Components integrate multiple ICs and 4- to 25-MHz external crystal oscillator system interfaces into one PSoC. Components are free Internal PLL clock generation up to 80 MHz embedded ICs represented by icons. Drag and drop component icons to design systems in PSoC Creator. Low-power internal oscillator at 1, 33, and 100 kHz Includes free GCC compiler, supports Keil/Arm MDK 32.768-kHz external watch crystal oscillator compiler 12 clock dividers routable to any peripheral or I/O Supports device programming and debugging Notes 1. The maximum storage temperature is 150 C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. This feature on select devices only. See Ordering Information on page 127 for details. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-84932 Rev. *N Revised November 27, 2019