Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comPSoC 6 MCU: CY8C61x6, CY8C61x7 Datasheet PSoC 61 MCU General Description PSoC 6 MCU is a high-performance, ultra-low-power and secure MCU platform, purpose-built for IoT applications. The CY8C61x6/7 product line, based on the PSoC 6 MCU platform, is a combination of a high-performance microcontroller with low-power flash technology, digital programmable logic, high-performance analog-to-digital conversion and standard communication and timing peripherals. Features 32-bit Dual CPU Subsystem Quad SPI (QSPI)/Serial Memory Interface (SMIF) Execute-In-Place (XIP) from external quad SPI Flash Note: In PSoC 61 the Cortex M0+ is reserved for system functions, and is not available for applications. On-the-fly encryption and decryption 150-MHz Arm Cortex -M4F (CM4) CPU with single-cycle 4-KB cache for greater XIP performance with lower power multiply, floating point, and memory protection unit (MPU) Supports single, dual, quad, dual-quad, and octal interfaces 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply with throughput up to 640 Mbps and MPU Segment LCD Drive Core logic operation at either 1.1 V or 0.9 V, depending on the Supports up to 99 segments and up to 8 commons part selected. See Ordering Information. Active CPU current slope with 1.1-V core operation Serial Communication Cortex-M4: 40 A/MHz Nine run-time configurable serial communication blocks Cortex-M0+: 20 A/MHz (SCBs) Active CPU current slope with 0.9-V core operation 2 Eight SCBs: configurable as SPI, I C, or UART Cortex-M4: 22 A/MHz 2 One Deep Sleep SCB: configurable as SPI or I C Cortex-M0+: 15 A/MHz USB full-speed device interface Two DMA controllers with 16 channels each Audio Subsystem Memory Subsystem 2 Two pulse density modulation (PDM) channels and one I S 1-MB application flash, 32-KB auxiliary flash (AUXflash), and channel with time division multiplexed (TDM) mode 32-KB supervisory flash (SFlash) read-while-write (RWW) Timing and Pulse-Width Modulation support. Two 8-KB flash caches, one for each CPU. Thirty-two timer/counter/pulse-width modulators (TCPWM) 288-KB SRAM with power and data retention control Center-aligned, edge, and pseudo-random modes One-time-programmable (OTP) 1-Kb eFuse array Comparator-based triggering of Kill signals Low-Power 1.7-V to 3.6-V Operation Programmable Analog Six power modes for fine-grained power management Deep Sleep mode current of 7 A with 64-KB SRAM retention 12-bit 1-Msps SAR ADC with differential and single-ended modes and 16-channel sequencer with result averaging On-chip Single-In Multiple Out (SIMO) DC-DC buck converter, <1 A quiescent current Two low-power comparators available in Deep Sleep and Hibernate modes Backup domain with 64 bytes of memory and real-time clock Built-in temperature sensor connected to ADC Flexible Clocking Options One 12-bit voltage-mode digital-to-analog converter (DAC) with 8-MHz Internal Main Oscillator (IMO) with 2% accuracy < 2-s settling time Ultra-low-power 32-kHz Internal Low-speed Oscillator (ILO) Two opamps with low-power operation modes On-chip crystal oscillators (16 to 35 MHz, and 32 kHz) Up to 100 Programmable GPIOs Phase-locked loop (PLL) for multiplying clock frequencies Two Smart I/O ports (16 I/Os) enable Boolean operations on Frequency-locked loop (FLL) for multiplying IMO frequency GPIO pins available during system Deep Sleep Integer and fractional peripheral clock dividers Programmable drive modes, strengths, and slew rates Six overvoltage-tolerant (OVT) pins Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-21414 Rev. *K Revised November 10, 2020