PSoC 6 MCU: PSoC 62 PRELIMINARY Datasheet Programmable System-on-Chip (PSoC ) General Description PSoC is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with ARM Cortex CPUs (single and multi-core). The PSoC 6 product family, based on an ultra low-power 40-nm platform, is a combination of a dual-core microcontroller with low-power Flash technology and digital programmable logic, high-performance analog-to-digital and digital-to-analog conversion, low-power comparators, and standard communication and timing peripherals. Features 32-bit Dual Core CPU Subsystem Flexible Clocking Options 150-MHz ARM Cortex-M4F CPU with single-cycle multiply On-chip crystal oscillators (High-speed, 4 to 33 MHz, and (Floating Point and Memory Protection Unit) Watch crystal, 32 kHz) 100-MHz Cortex M0+ CPU Phase-locked Loop (PLL) for multiplying clock frequencies User-selectable core logic operation at either 1.1 V or 0.9 V 8 MHz Internal Main Oscillator (IMO) with 1% accuracy Inter-processor communication supported in hardware Ultra low-power 32-kHz Internal Low-speed Oscillator (ILO) with 10% accuracy 8 KB 4-way set-associative Instruction Caches for the M4 and M0+ CPUs respectively IMO can be locked to 32 kHz WCO input for better accuracy Active CPU power consumption slope with 1.1-V core operation Frequency Locked Loop (FLL) for multiplying IMO frequency for the Cortex M4 is 40 A/MHz and 20 A/MHz for the Cortex Serial Communication M0+, both at 3.3-V chip supply voltage with the internal buck regulator Nine independent run-time reconfigurable serial communi- 2 cation blocks (SCBs), each is software configurable as I C, Active CPU power consumption slope with 0.9-V core operation SPI, or UART for the Cortex M4 is 22 A/MHz and 15 A/MHz for the Cortex M0+, both at 3.3-V chip supply voltage with the internal buck USB Full-Speed Dual-role Host and Device interface regulator Timing and Pulse-Width Modulation Two DMA controllers with 16 channels each Thirty-two 16-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks Flexible Memory Sub-system Center-aligned, Edge, and Pseudo-random modes 1 MB Application Flash with 32-KB EEPROM area and 32-KB Secure Flash Comparator-based triggering of Kill signals 128-bit wide Flash accesses reduce power Up to 104 Programmable GPIOs Flash Read-While-Write (RWW) allows updating the Flash Drive modes, strengths, and slew rates are programmable while executing from it Six overvoltage tolerant (OVT) pins SRAM with Selectable Retention Granularity 288-KB integrated SRAM Packages 32-KB retention boundaries (can retain 32K to 288K in 32K 124-BGA increments) 80-WLCSP One-Time-Programmable (OTP) E-Fuse memory for validation Audio Subsystem and security I2S Interface up to 192 kilosamples Word Clock Low-Power 1.7-V to 3.6-V Operation Two PDM channels for stereo digital microphones Active, Low-power Active, Sleep, Low-power Sleep, Deep Sleep, and Hibernate modes for fine-grained power QSPI Interface management Execute-In-Place (XIP) from external Quad SPI Flash Deep Sleep mode current with 64K SRAM retention is 7 A On-the-fly encryption and decryption with 3.3 V external supply and internal buck 4 KB QSPI cache for greater XIP performance with lower power On-chip Single-In Multiple Out (SIMO) DC-DC Buck converter, Supports 1, 2, 4, and Dual-Quad interfaces <1 A quiescent current Backup domain with 64 bytes of memory and Real-Time-Clock Errata: For information on silicon errata, see Errata on page 61. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-18449 Rev. *E Revised February 10, 2018 PSoC 6 MCU: PSoC 62 PRELIMINARY Datasheet Programmable Analog PSoC Creator Design Environment 12-bit 1 Msps SAR ADC with differential and single-ended Integrated Development Environment provides schematic modes and 16-Channel Sequencer with signal averaging design entry and build (with analog and digital automatic routing) and code development and debugging One 12-bit voltage mode DAC with < 5-s settling time Applications Programming Interface (API Component) for all Two opamps with low-power operation modes fixed-function and programmable peripherals Two low-power comparators that operate in Deep Sleep and Hibernate modes. Industry-Standard Tool Compatibility Built-in temp sensor connected to ADC After schematic entry, development can be done with ARM-based industry-standard development tools Programmable Digital Configure in PSoC Creator and export to ARM/Keil or IAR IDEs 12 programmable logic blocks, each with 8 Macrocells and an for code development and debugging 8-bit data path (called universal digital blocks or UDBs) Supports industry standard ARM Trace Emulation Trace Usable as drag-and-drop Boolean primitives (gates, registers), Module or as Verilog programmable blocks Security Built into Platform Architecture Cypress-provided peripheral component library using UDBs with common functions such as SDIO, Communication Multi-faceted secure architecture based on ROM-based root of Peripherals such as LIN, UART, SPI, I2C, S/PDIF, Waveform trust Generator, Pseudo-Random Sequence (PRS) generation, and Secure Boot uninterruptible until system protection attributes many other functions. are established Smart I/O (Programmable I/O) blocks enable Boolean Authentication during boot using hardware hashing operations on signals coming from, and going to, GPIO pins Step-wise authentication of execution images Two ports with Smart IO blocks, capability are provided these Secure execution of code in execute-only mode for protected are available during Deep Sleep routines Capacitive Sensing All Debug and Test ingress paths can be disabled Cypress Capacitive Sigma-Delta (CSD) provides best-in-class Cryptography Accelerators SNR, liquid tolerance, and proximity sensing Hardware acceleration for Symmetric and Asymmetric Mutual Capacitance sensing (Cypress CSX) with dynamic cryptographic methods (AES, 3DES, RSA, and ECC) and Hash usage of both Self and Mutual sensing functions (SHA-512, SHA-256) Wake on Touch with very low current True Random Number Generator (TRNG) function Cypress-supplied software component makes capacitive sensing design fast and easy Automatic hardware tuning (SmartSense) Energy Profiler Block that provides history of time spent in different power modes Allows software energy profiling to observe and optimize energy consumption Document Number: 002-18449 Rev. *E Page 2 of 66