Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comPSoC 6 MCU: CY8C63x6, CY8C63x7 Datasheet PSoC 63 MCU with Bluetooth LE General Description PSoC 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT applications. The PSoC 63 withBluetooth LE product line, based on the PSoC 6 MCU platform, is a combination of a high-performance microcontroller with low-power flash technology, digital programmable logic, high-performance analog-to-digital conversion and standard communication and timing peripherals. The PSoC 63 product line provides wireless connectivity with Bluetooth LE 5.0 compliance. Features 32-bit Dual CPU Subsystem Flexible Clocking Options 8-MHz Internal Main Oscillator (IMO) with 2% accuracy 150-MHz Arm Cortex -M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU) Ultra-low-power 32-kHz Internal Low-speed Oscillator (ILO) 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply On-chip crystal oscillators (16 to 35 MHz, and 32 kHz) and MPU Phase-locked loop (PLL) for multiplying clock frequencies User-selectable core logic operation at either 1.1 V or 0.9 V Frequency-locked loop (FLL) for multiplying IMO frequency Active CPU current slope with 1.1-V core operation Integer and fractional peripheral clock dividers Cortex-M4: 40 A/MHz Cortex-M0+: 20 A/MHz Quad SPI (QSPI)/Serial Memory Interface (SMIF) Active CPU current slope with 0.9-V core operation Execute-In-Place (XIP) from external quad SPI Flash Cortex-M4: 22 A/MHz On-the-fly encryption and decryption Cortex-M0+: 15 A/MHz 4-KB cache for greater XIP performance with lower power Two DMA controllers with 16 channels each Supports single, dual, quad, dual-quad, and octal interfaces with throughput up to 640 Mbps Memory Subsystem Segment LCD Drive 1-MB application flash, 32-KB auxiliary flash (AUXflash), and 32-KB supervisory flash (SFlash) read-while-write (RWW) Supports up to 83 segments and up to 8 commons support. Two 8-KB flash caches, one for each CPU. Serial Communication 288-KB SRAM with power and data retention control Nine run-time configurable serial communication blocks One-time-programmable (OTP) 1-Kb eFuse array (SCBs) 2 Eight SCBs: configurable as SPI, I C, or UART Bluetooth Low Energy Subsystem 2 One Deep Sleep SCB: configurable as SPI or I C 2.4-GHz RF transceiver with 50- antenna drive USB full-speed device interface Digital PHY Link Layer engine supporting master and slave modes Audio Subsystem Programmable TX power: up to 4 dBm 2 Two pulse density modulation (PDM) channels and one I S RX sensitivity: 95 dBm channel with time division multiplexed (TDM) mode RSSI: 4-dB resolution Timing and Pulse-Width Modulation 5.7-mA Tx (0 dBm) and 6.7 mA RX (2 Mbps) current with 3.3-V Thirty-two timer/counter/pulse-width modulators (TCPWM) supply and internal SIMO Buck converter Center-aligned, edge, and pseudo-random modes Link Layer engine supports four connections simultaneously Comparator-based triggering of Kill signals Supports 2 Mbps data rate Programmable Analog Low-Power 1.7-V to 3.6-V Operation 12-bit 1-Msps SAR ADC with differential and single-ended Six power modes for fine-grained power management modes and 16-channel sequencer with result averaging Deep Sleep mode current of 7 A with 64-KB SRAM retention Two low-power comparators available in Deep Sleep and On-chip Single-In Multiple Out (SIMO) DC-DC buck converter, Hibernate modes <1 A quiescent current Built-in temperature sensor connected to ADC Backup domain with 64 bytes of memory and real-time clock One 12-bit voltage-mode digital-to-analog converter (DAC) with < 2-s settling time Two opamps with low-power operation modes Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-18787 Rev. *O Revised June 30, 2021