PSoC 6 MCU: PSoC 63 with BLE Datasheet Programmable System-on-Chip (PSoC ) General Description PSoC is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with Arm Cortex CPUs (single and multi-core). The PSoC 63 product family, based on an ultra low-power 40-nm platform, is a combi- nation of a dual-core microcontroller with low-power Flash technology and digital programmable logic, high-performance analog-to-digital and digital-to-analog conversion, low-power comparators, and standard communication and timing peripherals. The PSoC 63 family provides wireless connectivity with BLE 5.0 compliance. Features 32-bit Dual Core CPU Subsystem Low-Power 1.7-V to 3.6-V Operation 150-MHz Arm Cortex-M4F CPU with single-cycle multiply Active, Low-power Active, Sleep, Low-power Sleep, Deep (Floating Point and Memory Protection Unit) Sleep, and Hibernate modes for fine-grained power management 100-MHz Cortex M0+ CPU with single-cycle multiply and MPU. Deep Sleep mode current with 64-KB SRAM retention is 7 A User-selectable core logic operation at either 1.1 V or 0.9 V with 3.3-V external supply and internal buck Inter-processor communication supported in hardware On-chip Single-In Multiple Out (SIMO) DC-DC Buck converter, 8 KB 4-way set-associative Instruction Caches for the M4 and <1 A quiescent current M0+ CPUs respectively Backup domain with 64 bytes of memory and Real-Time-Clock Active CPU power consumption slope with 1.1-V core operation for the Cortex M4 is 40 A/MHz and 20 A/MHz for the Cortex Flexible Clocking Options M0+, both at 3.3-V chip supply voltage with the internal buck regulator On-chip crystal oscillators (High-speed, 4 to 33 MHz, and Watch crystal, 32 kHz) Active CPU power consumption slope with 0.9-V core operation for the Cortex M4 is 22 A/MHz and 15 A/MHz for the Cortex Phase Locked Loop (PLL) for multiplying clock frequencies M0+, both at 3.3-V chip supply voltage with the internal buck regulator 8 MHz Internal Main Oscillator (IMO) with 2% accuracy Two DMA controllers with 16 channels each Ultra low-power 32 kHz Internal Low-speed Oscillator (ILO) with 10% accuracy Flash Memory Sub-system 1 MB Application Flash with 32-KB EEPROM area and 32-KB Frequency Locked Loop (FLL) for multiplying IMO frequency Secure Flash Serial Communication 128-bit wide Flash accesses reduce power SRAM with Selectable Retention Granularity Nine independent run-time reconfigurable serial communi- 2 cation blocks (SCBs), each is software configurable as I C, 288-KB integrated SRAM SPI, or UART 32-KB retention boundaries (can retain 32 KB to 288 KB in 32-KB increments) Timing and Pulse-Width Modulation One-Time-Programmable (OTP) E-Fuse memory for validation and security Thirty-two Timer/Counter Pulse-Width Modulator (TCPWM) blocks Bluetooth Low Energy (Bluetooth Smart) BT 5.0 Center-aligned, Edge, and Pseudo-random modes Subsystem 2.4-GHz RF transceiver with 50- antenna drive Comparator-based triggering of Kill signals Digital PHY Up to 78 Programmable GPIOs Link Layer engine supporting master and slave modes Drive modes, strengths, and slew rates are programmable Programmable output power: up to 4 dBm RX sensitivity: 95 dBm Six overvoltage tolerant (OVT) pins RSSI: 4-dB resolution Packages 5.7 mA TX (0 dBm) and 6.7 mA RX (2 Mbps) current with 3.3-V battery and internal SIMO Buck converter 116-BGA and 104-MCSP packages with PSoC 6 and BLE Radio Link Layer engine supports four connections simultaneously Supports 2 Mbps LE data rate Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-18787 Rev. *G Revised July 17, 2018 PSoC 6 MCU: PSoC 63 with BLE Datasheet Audio Subsystem Energy Profiler I2S Interface up to 192 kilosamples (ksps) Word Clock Block that provides history of time spent in different power modes Two PDM channels for stereo digital microphones Allows software energy profiling to observe and optimize QSPI Interface energy consumption Execute-In-Place (XIP) from external Quad SPI Flash PSoC Creator Design Environment On-the-fly encryption and decryption Integrated Development Environment provides schematic 4-KB QSPI cache for greater XIP performance with lower power design entry and build (with analog and digital automatic Supports 1, 2, 4, and Dual-Quad interfaces routing) and code development and debugging Applications Programming Interface (API Component) for all Programmable Analog fixed-function and programmable peripherals 12-bit 1 Msps SAR ADC with differential and single-ended Bluetooth Smart Component (BLE4.2 compliant protocol stack) modes and Sequencer with signal averaging with Application level function calls and Profiles One 12-bit voltage mode DAC with < 5-s settling time Two opamps with low-power operation modes Industry-Standard Tool Compatibility Two low-power comparators that operate in Deep Sleep and After schematic entry, development can be done with Hibernate modes. Arm-based industry-standard development tools Built-in temp sensor connected to ADC Configure in PSoC Creator and export to Arm/Keil or IAR IDEs for code development and debugging Programmable Digital Supports industry standard Arm Trace Emulation Trace Module 12 programmable logic blocks, each with 8 Macrocells and an 8-bit data path (called universal digital blocks or UDBs) Security Built into Platform Architecture Usable as drag-and-drop Boolean primitives (gates, registers), Multi-faceted secure architecture based on ROM-based root of or as Verilog programmable blocks trust Cypress-provided peripheral component library using UDBs to implement functions such as Communication peripherals (for Secure Boot uninterruptible until system protection attributes 2 example, LIN, UART, SPI, I C, S/PDIF and other protocols), are established Waveform Generators, Pseudo-Random Sequence (PRS) Authentication during boot using hardware hashing generation, and many other functions. Smart I/O (Programmable I/O) blocks enable Boolean Step-wise authentication of execution images operations on signals coming from, and going to, GPIO pins Secure execution of code in execute-only mode for protected Two ports with Smart IO blocks, capability are provided these routines are available during Deep Sleep All Debug and Test ingress paths can be disabled Capacitive Sensing Cryptography Accelerators Cypress Capacitive Sigma-Delta (CSD) provides best-in-class SNR, liquid tolerance, and proximity sensing Hardware acceleration for Symmetric and Asymmetric Mutual Capacitance sensing (Cypress CSX) with dynamic cryptographic methods (AES, 3DES, RSA, and ECC) and Hash usage of both Self and Mutual sensing functions (SHA-512, SHA-256) Wake on Touch with very low current True Random Number Generator (TRNG) function Cypress-supplied software component makes capacitive sensing design fast and easy Automatic hardware tuning (SmartSense) Document Number: 002-18787 Rev. *G Page 2 of 63