CY8C9520A CY8C9540A CY8C9560A 20-, 40-, and 60-Bit I/O Expander with EEPROM Features Overview 2 I C interface logic electrically compatible with SMBus The CY8C95xxA is a multi-port I/O expander with on board user available EEPROM and several PWM outputs. All devices in this Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A) family operate identically but differ in I/O pins, number of PWMs, I/O data pins independently configurable as inputs, outputs, and internal EEPROM size. Bi-directional input/outputs, or PWM outputs 2 The CY8C95xxA operates as two I C slave devices. The first 2 4/8/16 PWM sources with 8-bit resolution device is a multi port I/O expander (single I C address to access 2 all ports through registers). The second device is a serial Extendable soft addressing algorithm allowing flexible I C EEPROM. Dedicated configuration registers can be used to address configuration disable the EEPROM. The EEPROM uses 2-byte addressing to Internal 3-/11-/27-Kbyte EEPROM support the 28 Kbyte EEPROM address space. The selected 2 device is defined by the most significant bits of the I C address User default storage, I/O port settings in internal EEPROM or by specific register addressing. Optional EEPROM write disable (WD) input The I/O expander s data pins can be independently assigned as inputs, outputs, quasi-bidirectional input/outputs or PWM Interrupt output indicates input pin level changes and pulse outputs. The individual data pins can be configured as open drain width modulator (PWM) state changes or collector, strong drive (10 mA source, 25 mA sink), resistively Internal power on reset (POR) pulled up or down, or high impedance. The factory default configuration is pulled up internally. Internal configurable watchdog timer The system master writes to the I/O configuration registers 2 through the I C bus. Configuration and output register settings are storable as user defaults in a dedicated section of the Top Level Block Diagram EEPROM. If user defaults were stored in EEPROM, they are restored to the ports at power up. While this device can share the 2 WD EEPROM bus with SMBus devices, it can only communicate with I C 2 2 User User masters. The I C slave in this device requires that the I C master Settings Available supports clock stretching. Area Area There is one dedicated pin that is configured as an interrupt output (INT) and can be connected to the interrupt logic of the Clocks system master. This signal can inform the system master that there is incoming data on its ports or that the PWM output state 32 kHz GPort 0 8 Bit IO was changed. 24 MHz 1.5 MHz 5 Bit IO The EEPROM is byte readable and supports byte-by-byte GPort 1 3 Bit IO writing. A pin can be configured as an EEPROM Write Disable or A4-A6 93.75 kHz (WD) input that blocks write operations when set high. The 4 Bit IO GPort 2 configuration registers can also disable EEPROM operations. Divider (1-255) or A1-A3, WD6 The CY8C95xxA has one fixed address pin (A0) and up to six Control PWM 0 GPort 3 8 Bit IO Unit additional pins (A1-A6), which allow up to 128 devices to share 2 a common two wire I C data bus. The Extendable Soft Addressing algorithm provides the option to choose the number PWM 15 GPort 7 8 Bit IO of pins needed to assign the desired address. Pins not used for address bits are available as GPIO pins. There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A) SCL INT independently configurable 8-bit PWMs. These PWMs are listed SDA as PWM0-PWM15. Each PWM can be clocked by one of six V Power-on-Reset A0 dd available clock sources. V ss Errata: For information on silicon errata, see Errata on page 30. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-12036 Rev. *L Revised April 27, 2017 CY8C9520A CY8C9540A CY8C9560A Contents Architecture ......................................................................3 Commands Description ................................................. 14 Applications .................................................................3 Store Config to E2 POR Defaults Cmd (01h) ............ 14 Device Access Addressing ..............................................4 Restore Factory Defaults Cmd (02h) ......................... 14 Serial EEPROM Device ...............................................4 Write E2 POR Defaults Cmd (03h) ............................ 14 Multi Port I/O Device ...................................................4 Read E2 POR Defaults Cmd (04h) ........................... 15 Pinouts ..............................................................................5 Write Device Config Cmd (05h) ................................. 15 28-Pin Part Pinout .......................................................5 Read Device Config Cmd (06h) ................................ 15 48-Pin Part Pinout .......................................................6 Reconfigure Device Cmd (07h) ................................. 15 100-Pin Part Pinout .....................................................7 Electrical Specifications ................................................ 16 Pin Descriptions ...............................................................9 Absolute Maximum Ratings ....................................... 16 Extendable Soft Addressing ........................................9 Operating Temperature ............................................. 16 Interrupt Pin (INT) ........................................................9 DC Electrical Characteristics ..................................... 17 Write Disable Pin (WD) ...............................................9 AC Electrical Characteristics ..................................... 19 External Reset Pin (XRES) .........................................9 Packaging Dimensions .................................................. 21 Working with PWMs ....................................................9 Thermal Impedances ................................................. 23 Register Mapping Table .................................................11 Solder Reflow Specifications ..................................... 23 Register Descriptions ....................................................11 Features and Ordering Information ..............................24 Input Port Registers (00h07h) .................................11 Ordering Code Definitions ......................................... 24 Output Port Registers (08h0Fh) ..............................11 Acronyms ........................................................................25 Int. Status Port Registers (10h17h) .........................12 Reference Documents .................................................... 25 Port Select Register (18h) .........................................12 Document Conventions ................................................. 25 Interrupt Mask Port Register (19h) ............................12 Units of Measure ....................................................... 25 Select PWM Register (1Ah) ......................................12 Numeric Conventions .................................................... 25 Inversion Register (1Bh) ............................................12 Numeric Naming ........................................................ 25 Port Direction Register (1Ch) ....................................12 Glossary ..........................................................................26 Drive Mode Registers (1Dh23h) ..............................12 Errata ...............................................................................30 PWM Select Register (28h) .......................................12 Part Numbers Affected .............................................. 30 Config (29h) ...............................................................13 Qualification Status ................................................... 30 Period Register (2Ah) ................................................13 Errata Summary ........................................................ 30 Pulse Width Register (2Bh) .......................................13 Document History Page ................................................. 31 Divider Register (2Ch) ...............................................13 Sales, Solutions, and Legal Information ...................... 32 Enable Register (2Dh) ...............................................13 Worldwide Sales and Design Support ....................... 32 Device ID/Status Register (2Eh) ...............................13 Products ....................................................................32 Watchdog Register (2Fh) ..........................................14 PSoC Solutions ...................................................... 32 Command Register (30h) ..........................................14 Cypress Developer Community ................................. 32 Technical Support ..................................................... 32 Document Number: 38-12036 Rev. *L Page 2 of 32