Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9A110A/CY9A110 Series 32-bit Arm Cortex -M3 FM3 Microcontroller The CY9A110A/CY9A110 Series are highly integrated 32-bit microcontrollers that target for high-performance and cost-sensitive embedded control applications. The CY9A110A Series are based on the Arm Cortex -M3 Processor and on-chip Flash memory and SRAM, and peripheral functions, 2 including Motor Control Timers, ADCs, Communication Interfaces (UART, CSIO, I C, LIN). The products which are described in this datasheet are placed into TYPE1 product categories in FM3 Family Peripheral Manual. Features 32-bit Arm Cortex-M3 Core UART Processor version: r2p1 Full duplex double buffer Up to 40 MHz Frequency Operation Selection with or without parity supported Integrated Nested Vectored Interrupt Controller (NVIC): 1 Built-in dedicated baud rate generator NMI (non-maskable interrupt) and 48 peripheral interrupts External clock available as a serial clock and 16 priority levels Hardware Flow control: Automatically control the 24-bit System timer (Sys Tick): System timer for OS task transmission by CTS/RTS (only ch.4)* management Various error detection functions available (parity errors, On-chip Memories framing errors, and overrun errors) *: CY9AF111LA, F112LA, F114LA, F112L and F114L do not Flash memory support Hardware Flow control Up to 512 Kbyte CSIO Read cycle: 0 wait-cycle Full duplex double buffer Security function for code protection Built-in dedicated baud rate generator SRAM Overrun error detection function available This Series contain a total of up to 32 Kbyte on-chip SRAM. LIN On-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D- LIN protocol Rev.2.1 supported code bus of Cortex-M3 core. SRAM1 is connected to System Full duplex double buffer bus. Master/Slave mode supported SRAM0: Up to 16 Kbytes LIN break field generation (can be changed 13- 16bit length) SRAM1: Up to 16 Kbytes LIN break delimiter generation (can be changed 1 - 4bit Multi-function Serial Interface (Max 8 channels) length) 4 channels with 16 steps9bit FIFO (ch.4-ch.7), 4 channels Various error detection functions available (parity errors, without FIFO (ch.0-ch3) framing errors, and overrun errors) 2 Operation mode is selectable from the followings for each I C channel. Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) UART supported CSIO LIN 2 I C Cypress Semiconductor Corporation An Infineon Technologies Company 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-04672 Rev. *F Revised April 29, 2020