Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9B120M Series 32-bit Arm Cortex -M3 FM3 Microcontroller The CY9B120M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the Arm Cortex -M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions 2 such as various timers, ADCs, DACs and Communication Interfaces (UART, CSIO, I C, LIN). The products which are described in this data sheet are placed into TYPE9 product categories in FM3 Family Peripheral Manual. Features 32-bit Arm Cortex -M3 Core UART Processor version: r2p1 Full duplex double buffer Up to 72 MHz Frequency Operation Selection with or without parity supported Integrated Nested Vectored Interrupt Controller (NVIC): 1 Built-in dedicated baud rate generator NMI (non-maskable interrupt) and 48 peripheral interrupts External clock available as a serial clock and 16 priority levels Hardware Flow control: Automatically control the 24-bit System timer (Sys Tick): System timer for OS task transmission/reception by CTS/RTS (only ch.4) management Various error detection functions available (parity errors, On-chip Memories framing errors, and overrun errors) Flash memory CSIO Dual operation Flash memory Full duplex double buffer Dual Operation Flash memory has the upper bank and the Built-in dedicated baud rate generator lower bank. So, this series could implement erase, write and read Overrun error detection function available operations for each bank simultaneously. LIN Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank) LIN protocol Rev.2.1 supported Work area: 32 Kbytes (lower bank) Full duplex double buffer Read cycle: 0 wait-cycle Master/Slave mode supported Security function for code protection LIN break field generation (can be changed to 13 to 16-bit SRAM length) This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus LIN break delimiter generation (can be changed to 1 to 4-bit and D-code bus of Cortex-M3 core. SRAM1 is connected to length) System bus. Various error detection functions available (parity errors, framing errors, and overrun errors) SRAM0: Up to 16 Kbytes 2 I C SRAM1: Up to 16 Kbytes Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps) Multi-function Serial Interface (Max eight channels) supported 4 channels with 16 stepsx9-bit FIFO (ch.0/1/3/4), 4 channels without FIFO (ch.2/5/6/7) Operation mode is selectable from the followings for each channel. UART CSIO LIN 2 I C Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05655 Rev. *I Revised April 15, 2021