Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY9B310R Series 32-bit Arm Cortex -M3 FM3 Microcontroller The CY9B310R Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and has 2 peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I C, LIN). The products which are described in this data sheet are placed into TYPE4 product categories in FM3 Family Peripheral Manual. Features External Bus Interface 32-bit Arm Cortex-M3 Core Processor version: r2p1 Supports SRAM, NOR and NAND Flash device Up to 144 MHz Frequency Operation Up to 8 chip selects Memory Protection Unit (MPU): improves the reliability of an 8-/16-bit Data width embedded system Up to 25-bit Address bit Integrated Nested Vectored Interrupt Controller (NVIC): 1 Maximum area size: Up to 256 Mbytes NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels Supports Address/Data multiplex 24-bit System timer (Sys Tick): System timer for OS task Supports external RDY input management USB Interface On-chip Memories USB interface is composed of Device and Host. Flash memory PLL for USB is built-in, USB clock can be generated by These series are based on two independent on-chip Flash multiplication of Main clock. memories. USB device MainFlash USB2.0 Full-Speed supported Up to 512 Kbyte Max 6 EndPoint supported Built-in Flash Accelerator System with 16 Kbyte trace EndPoint 0 is control transfer buffer memory EndPoint 1, 2 can be selected Bulk-transfer, The read access to Flash memory can be achieved without Interrupt-transfer or Isochronous-transfer wait cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent EndPoint 3 to 5 can be selected Bulk-transfer or access to Flash memory can be obtained by Flash Interrupt-transfer Accelerator System. EndPoint 1 to 5 is comprised Double Buffer Security function for code protection The size of each EndPoint is as follows. WorkFlash EndPoint 0, 2 to 5: 64 bytes 32 Kbyte EndPoint 1: 256 bytes Read cycle USB host 4 wait-cycle: the operation frequency more than 72 MHz USB2.0 Full/Low-speed supported 2 wait-cycle: the operation frequency more than 40 MHz, Bulk-transfer, interrupt-transfer and Isochronous-transfer and to 72 MHz support 0 wait-cycle: the operation frequency to 40 MHz USB Device connected/dis-connected automatically detect Security function is shared with code protection IN/OUT token handshake packet automatically SRAM Max 256-byte packet-length supported Wake-up function supported This Series contain a total of up to 64 Kbyte on-chip SRAM. This is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. SRAM0: Up to 32 Kbyte SRAM1: Up to 32 Kbyte Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-05619 Rev. *E Revised May 20, 2019