Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comSHM 35-Series: SHM35920-M Family Datasheet System Hardware Manager (SHM) General Description SHM 35-Series is a scalable and reconfigurable platform architecture for a family of full programmable embedded system controllers with an ARM Cortex-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The SHM35920-M product family, based on this platform architecture, is a combination of a microcontroller with digital programmable logic, programmable analog, programmable interconnect, high-performance analog-to-digital conversion, opamps with comparator mode, and standard communication and timing peripherals. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design. Features 32-bit MCU Subsystem Timing and Pulse-Width Modulation 24-MHz ARM Cortex-M0 CPU with single-cycle multiply Eight 16-bit timer/counter pulse-width modulator (TCPWM) blocks Up to 128 kB of flash with Read Accelerator Up to 16 kB of SRAM Center-aligned, Edge, and Pseudo-random modes DMA engine with 8 channels Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Programmable Analog Four opamps that operate in Deep Sleep mode at very low Package Options current levels 68-pin QFN package All opamps have reconfigurable high current pin-drive, Up to 55 programmable GPIOs high-bandwidth internal drive, ADC input buffering, and Comparator modes with flexible connectivity allowing input GPIO pins can be LCD, analog, or digital connections to any pin Drive modes, strengths, and slew rates are programmable Two current DACs (IDACs) for general-purpose applications on any pin Pin compatible with select PSoC 4 devices Two low-power comparators that operate in Deep Sleep mode Packages assembled with Ultra Low Alpha (ULA) mold 12-bit SAR ADC with 806-Ksps conversion rate compounds and materials to reduce rate of alpha particle related failures Low Power 1.71 to 5.5 V Operation PSoC Creator Design Environment 20-nA Stop Mode with GPIO pin wakeup Hibernate and Deep Sleep modes allow wakeup-time versus Integrated Development Environment (IDE) provides power trade-offs schematic design entry and build (with analog and digital automatic routing) Segment LCD Drive Applications Programming Interface (API component) for all LCD drive supported on all pins (common or segment) fixed-function and programmable peripherals Operates in Deep Sleep mode with 4 bits per pin memory Industry-Standard Tool Compatibility Serial Communication After schematic entry, development can be done with ARM-based industry-standard development tools Four independent run-time reconfigurable serial 2 communication blocks (SCBs) with reconfigurable I C, SPI, or UART functionality Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-13261 Rev. *B Revised December 5, 2017