EVAL_1EDF_G1_HB_GAN Infineon

AN 1811 PL52 1811 234307 CoolGaN 600 V half-bridge evaluation platform featuring EiceDRIVER GaN About this document Authors: Eric Persson, Yalcin Haksoz Ordering code: EVAL 1EDF G1B HB GAN Scope and purpose This application note explains how to setup and use the CoolGaN 600 V half-bridge evaluation board. The board features a half-bridge of 70 m GaN power transistors, a pair of EiceDRIVER GaN gate drivers, and isolated power supplies for the gate drivers along with input logic that provides adjustable deadtime. Using an external inductor, the board can be configured for buck or boost-mode, double-pulse testing or continuous PWM operation, hard or soft-switching at power levels to several kW and frequencies up to MHz range. Intended audience This document is intended for power electronic engineers and designers who are already familiar with MOSFET or IGBT-based converters, inverters and gate drivers, who are interested in looking at the similarities and differences of GaN power transistors compared to their silicon counterparts. Figure 1 Front and back view of the CoolGaN half-bridge evaluation platform Application Note Please read the Important Notice and Warnings at the end of this document V 1.1 www.infineon.com/eval-1edf-g1b-hb-gan page 1 of 23 2020-11-09 CoolGaN 600 V half-bridge evaluation platform featuring EiceDRIVER GaN Table of contents Table of contents About this document ....................................................................................................................... 1 Table of contents ............................................................................................................................ 2 1 Introduction .......................................................................................................................... 3 1.1 Evaluation board specifications ............................................................................................................. 3 2 Functional description ............................................................................................................ 4 3 Circuit description .................................................................................................................. 5 3.1 Input Logic and deadtime generator ...................................................................................................... 5 3.2 Isolated gate driver power supply .......................................................................................................... 6 3.2.1 Gate driver power supply transformer .............................................................................................. 6 3.3 Gate drive circuit ..................................................................................................................................... 7 3.4 Half-bridge output circuit ....................................................................................................................... 8 4 Setup and use ........................................................................................................................ 9 4.1 Test equipment needed .......................................................................................................................... 9 4.2 Connections to the terminal block ......................................................................................................... 9 4.2.1 Connections for double-pulse testing ............................................................................................. 10 4.2.2 Connections for buck topology ....................................................................................................... 10 4.2.3 Connections for boost topology ...................................................................................................... 12 4.3 Input PWM generator connections and settings .................................................................................. 13 4.4 Measurement points ............................................................................................................................. 13 4.5 Power-up and power-down sequencing .............................................................................................. 13 4.6 Verifying and adjusting deadtime ......................................................................................................... 14 4.7 Test inductor recommendation ............................................................................................................ 15 4.8 Initial checkout ...................................................................................................................................... 16 4.9 Operation at high power levels ............................................................................................................. 17 5 Complete schematic .............................................................................................................. 18 6 PCB layout ............................................................................................................................ 19 7 Bill of materials ..................................................................................................................... 21 8 Revision history .................................................................................................................... 22 Application Note 2 of 23 V 1.1 2020-11-09