EVAL3KW2LLCC720TOBO1 Infineon

AN 201609 PL52 004 3 kW dual-phase LLC evaluation board Using 600 V CoolMOS C7 and digital control by XMC4400 Authors: Francesco Di Domenico David Meneses Herrera Stefano de Filippis About this document Scope and purpose This document describes the design and performance of a 3 kW dual-phase LLC evaluation board intended for use in the isolated HV DC-DC stage of a Switch Mode Power Supply (SMPS) for telecom and industrial applications. This is a high performance example with a complete Infineon solution, including HV and LV power MOSFETs, controllers, and drivers, demonstrating a very effective way to design the HV DC-DC stage of a telecom rectifier or Industrial SMPS fulfilling the highest standard of efficiency and reliability. The additional benefit of a very flat efficiency plot is also achieved through a mix of proper control techniques and best-in class power device selection. Key Infineon products used to achieve this performance level include: 600 V CoolMOS C7 superjunction MOSFET Isolated gate driver 1EDI60N12AF SyncRec MOSFETs OptiMOS BSC093N15NS5 Advanced dual channel gate driver 2EDN7524 XMC4400 microcontroller Bias QR flyback controller ICE2QR2280Z As well as design information and documentation of the LLC converter, the reader will receive additional information on how the 600 V CoolMOS C7 behaves in LLC applications and the associated benefits, how the high performance magnetics design can be approached, and insights on how to develop dual-phase LLC converters in similar power ranges adapted to specific requirements. Intended audience This document is intended for design engineers who wish to evaluate high performance topologies for high power SMPS converters, and develop an understanding of the design process and how to apply the multi-phase LLC design methods to their own system applications. Note: General knowledge about the resonant HB LLC converter principle of operation is required for proper comprehension of the concepts reported in this paper. Application Note Please read the Important Notice and Warnings at the end of this document V1.0 www.infineon.com 2016-10-12 3 kW dual-phase LLC evaluation board Using 600 V CoolMOS C7 and digital control by XMC4400 Introduction Table of contents About this document ....................................................................................................................... 1 Table of contents ............................................................................................................................ 2 1 Introduction .................................................................................................................. 4 2 Dual-phase HB LLC design concept .................................................................................. 5 2.1 Current sharing and phase shedding ..................................................................................................... 5 2.1.1 The design challenges ........................................................................................................................ 5 2.1.2 The proposed implementation .......................................................................................................... 9 2.2 Reliability features ................................................................................................................................ 12 2.3 Graphical User Interface (GUI) .............................................................................................................. 15 3 Board description ......................................................................................................... 16 3.1 Main requirements in the technical specification ................................................................................ 16 3.2 General overview of the final design .................................................................................................... 16 3.3 Infineon components ............................................................................................................................ 17 TM 3.3.1 Primary HV MOSFETs 600 V CoolMOS C7 ...................................................................................... 17 3.3.2 Isolated gate drive 1EDI60N12AF ..................................................................................................... 18 3.3.3 SyncRec MOSFETs OptiMOS BSC093N15NS5 ............................................................................... 18 3.3.4 Advanced dual channel gate drive 2EDN7524 ................................................................................ 19 3.3.5 XMC4400 microcontroller ................................................................................................................ 19 3.3.6 Bias QR flyback controller ICE2QR2280Z ........................................................................................ 20 3.4 Board schematics .................................................................................................................................. 21 3.4.1 LLC switching power stage .............................................................................................................. 21 3.4.2 Synchronous rectification and secondary stage............................................................................. 22 3.4.3 Control board ................................................................................................................................... 23 3.4.4 Bias board (auxiliary converter) ...................................................................................................... 24 3.5 Magnetic components........................................................................................................................... 25 3.5.1 HB LLC main transformer ................................................................................................................ 25 3.5.2 LLC resonant choke .......................................................................................................................... 26 3.5.3 Auxiliary transformer ....................................................................................................................... 27 4 Digital control features ................................................................................................. 28 4.1 Resources used and implementation concept .................................................................................... 28 4.1.1 Resources (peripherals) used .......................................................................................................... 28 4.1.2 Implementation concept ................................................................................................................. 29 4.2 Current-sharing and phase shedding ................................................................................................... 31 4.3 Hard-commutation prevention and capacitive mode detection ........................................................ 34 4.3.1 Hard-commutation prevention ....................................................................................................... 34 4.3.2 Capacitive mode detection and prevention ................................................................................... 36 4.4 Protections ............................................................................................................................................ 37 4.4.1 Over-current-protection .................................................................................................................. 37 4.4.2 Input and output voltage monitoring ............................................................................................. 38 4.4.3 Other protections ............................................................................................................................. 39 4.5 Burst mode and SR management ......................................................................................................... 39 4.6 Adaptive dead time ............................................................................................................................... 41 4.7 Loop compensation parameters .......................................................................................................... 41 4.8 Graphical User Interface (GUI) .............................................................................................................. 42 5 Performance evaluation ................................................................................................ 44 5.1 Waveforms captured in significant operation modes .......................................................................... 44 5.2 Efficiency plot ........................................................................................................................................ 48 6 Conclusion ................................................................................................................... 51 Application Note 2 V1.0 2016-10-12