IR2104SPBF Infineon

Data Sheet No. PD60046-S ( ) & (PbF) IR2104 S HALF-BRIDGE DRIVER Features Product Summary Floating channel designed for bootstrap operation V 600V max. OFFSET Fully operational to +600V Tolerant to negative transient voltage I +/- 130 mA / 270 mA O dV/dt immune Gate drive supply range from 10 to 20V V 10 - 20V OUT Undervoltage lockout 3.3V, 5V and 15V input logic compatible t (typ.) 680 & 150 ns on/off Cross-conduction prevention logic Internally set deadtime Deadtime (typ.) 520 ns High side output in phase with input Shut down input turns off both channels Packages Matched propagation delay for both channels Also available LEAD-FREE Description The IR2104(S) are high voltage, high speed power 8 Lead SOIC MOSFET and IGBT drivers with dependent high and low 8 Lead PDIP IR2104S side referenced output channels. Proprietary HVIC and IR2104 latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates from 10 to 600 volts. Typical Connection up to 600V V CC V V CC B IN IN HO TO SD SD V LOAD S COM LO (Refer to Lead Assignment for correct pin configuration) This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1( ) & (PbF) S IR2104 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High side floating absolute voltage -0.3 625 B V High side floating supply offset voltage V - 25 V + 0.3 S B B V High side floating output voltage V - 0.3 V + 0.3 HO S B V V Low side and logic fixed supply voltage -0.3 25 CC V Low side output voltage -0.3 V + 0.3 LO CC V Logic input voltage (IN & SD) -0.3 V + 0.3 IN CC dV /dt Allowable offset supply voltage transient 50 V/ns s P Package power dissipation T +25C (8 lead PDIP) 1.0 D A W (8 lead SOIC) 0.625 Rth Thermal resistance, junction to ambient (8 lead PDIP) 125 JA C/W (8 lead SOIC) 200 T Junction temperature 150 J C T Storage temperature -55 150 S T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The V offset rating is tested with all supplies biased at 15V differential. S Symbol Definition Min. Max. Units V High side floating supply absolute voltage V + 10 V + 20 B S S V High side floating supply offset voltage Note 1 600 S V High side floating output voltage V V HO S B V V Low side and logic fixed supply voltage 10 20 CC V Low side output voltage 0 V LO CC V Logic input voltage (IN & SD)0V IN CC C T Ambient temperature -40 125 A Note 1: Logic operational for V of -5 to +600V. Logic state held for V of -5V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). www.irf.com 2