IR21091STRPBF Infineon

Data Sheet No. PD60191 revD ( ) & (PbF) IR21091 S HALF-BRIDGE DRIVER Product Summary Features Floating channel designed for bootstrap operation V 600V max. Fully operational to +600V OFFSET Tolerant to negative transient voltage I +/- 120 mA / 250 mA O dV/dt immune Gate drive supply range from 10 to 20V V 10 - 20V OUT Undervoltage lockout for both channels 3.3V, 5V and 15V input logic compatible ton/off (typ.) 680 & 170 ns Cross-conduction prevention logic Matched propagation delay for both channels Dead time 500 ns High side output in phase with IN input (programmable up to 5uS) Logic and power ground +/- 5V offset. Internal 500ns dead-time, and programmable up to 5us with one external R resistor DT Lower di/dt gate driver for better noise immunity Packages The dual function DT/SD pin input turns off both channels. Available in Lead-Free Description The IR21091(S) are high voltage, high speed power MOSFET and IGBT drivers with dependant high and 8 Lead PDIP 8 Lead SOIC low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable rugge- dized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross- conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Typical Connection up to 600V V CC V V CC B IN IN HO TO SD DT/SD V S LOAD COM LO IR21091(S) (Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1( ) & (PbF) S IR21091 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High side floating absolute voltage -0.3 625 B V High side floating supply offset voltage V - 25 V + 0.3 S B B V High side floating output voltage V - 0.3 V + 0.3 HO S B V Low side and logic fixed supply voltage -0.3 25 CC V V Low side output voltage -0.3 V + 0.3 LO CC DT/SD Programmable dead-time and shut-down pin voltage V - 0.3 V + 0.3 SS CC V Logic input voltage V - 0.3 V + 0.3 IN SS CC dV /dt Allowable offset supply voltage transient 50 V/ns S P Package power dissipation T +25C (8 Lead PDIP) 1.0 D A W (8 Lead SOIC) 0.625 Rth Thermal resistance, junction to ambient (8 Lead PDIP) 125 JA C/W (8 Lead SOIC) 200 T Junction temperature 150 J T Storage temperature -50 150 C S T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V offset rating are tested with all supplies biased at 15V differential. S Symbol Definition Min. Max. Units VB High side floating supply absolute voltage V + 10 V + 20 S S V High side floating supply offset voltage Note 1 600 S V High side floating output voltage V V HO S B V Low side and logic fixed supply voltage 10 20 CC V V Low side output voltage 0 V LO CC V Logic input voltage V V IN SS CC DT/SD Programmable dead-time and shut-down pin voltage V V SS CC T Ambient temperature -40 125 C A Note 1: Logic operational for V of -5 to +600V. Logic state held for V of -5V to -V (Please refer to the Design Tip S S BS. DT97-3 for more details). 2 www.irf.com