IR2111PbF Infineon

Data Sheet No. PD60028-M ( ) ( ) IR2111 S & PbF HALF-BRIDGE DRIVER Features Product Summary Floating channel designed for bootstrap operation V 600V max. OFFSET Fully operational to +600V Tolerant to negative transient voltage I +/- 200 mA / 420 mA dV/dt immune O Gate drive supply range from 10 to 20V Undervoltage lockout for both channels V 10 - 20V OUT CMOS Schmitt-triggered inputs with pull-down Matched propagation delay for both channels t (typ.) 750 & 150 ns on/off Internally set deadtime High side output in phase with input Deadtime (typ.) 650 ns Also available LEAD-FREE Description Packages The IR2111(S) is a high voltage, high speed power MOSFET and IGBT driver with dependent high and low side referenced output channels designed for half- bridge applications. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic input is compatible with standard CMOS outputs. The output drivers feature a high pulse current buffer stage designed for minimum 8-Lead PDIP 8-Lead SOIC driver cross-conduction. Internal deadtime is provided to avoid shoot-through in the output half-bridge. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Typical Connection up to 600V V CC V V CC B IN IN HO TO COM V S LOAD LO (Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1( ) & (PbF) IR2111 S Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in figures 7 through 10. Symbol Definition Min. Max. Units V High side floating supply voltage -0.3 625 B V High side floating supply offset voltage V - 25 V + 0.3 S B B V High side floating output voltage V - 0.3 V + 0.3 HO S B V V Low side and logic fixed supply voltage -0.3 25 CC V Low side output voltage -0.3 V + 0.3 LO CC V Logic input voltage -0.3 V + 0.3 IN CC dV /dt Allowable offset supply voltage transient (figure 2) 50 V/ns s P Package power dissipation T +25C (8 Lead PDIP) 1.0 D A W (8 lead SOIC) 0.625 Rth Thermal resistance, junction to ambient (8 lead PDIP) 125 JA C/W (8 lead SOIC) 200 T Junction temperature 150 J C T Storage temperature -55 150 S T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V offset rating is tested with all supplies biased at 15V differential. S Symbol Definition Min. Max. Units V High side floating supply absolute voltage V + 10 V + 20 B S S V High side floating supply offset voltage Note 1 600 S V High side floating output voltage V V HO S B V V Low side and logic fixed supply voltage 10 20 CC V Low side output voltage 0 V LO CC V Logic input voltage 0 V IN CC C T Ambient temperature -40 125 A Note 1: Logic operational for V of -5 to +600V. Logic state held for V of -5V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). 2 www.irf.com