IR2112SPBF Infineon

Data Sheet No. PD60026 revS ( )( ) IR2112 -1-2 S PbF HIGH AND LOW SIDE DRIVER Features Product Summary Floating channel designed for bootstrap operation V 600V max. OFFSET Fully operational to +600V Tolerant to negative transient voltage I +/- 200 mA / 420 mA dV/dt immune O Gate drive supply range from 10 to 20V Undervoltage lockout for both channels V 10 - 20V OUT 3.3V logic compatible Separate logic supply range from 3.3V to 20V t (typ.) 125 & 105 ns on/off Logic and power ground 5V offset CMOS Schmitt-triggered inputs with pull-down Delay Matching 30 ns Cycle by cycle edge-triggered shutdown logic Matched propagation delay for both channels Packages Outputs in phase with inputs Description The IR2112(S) is a high voltage, high speed power MOSFET and IGBT driver with independent high and 16-Lead SOIC (wide body) low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable rugge- 14-Lead PDIP dized monolithic construction. Logic inputs are com- patible with standard CMOS or LSTTL outputs, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts. Typical Connection (Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1( )( ) IR2112 -1-2 S PbF Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 28 through 35. Symbol Definition Min. Max. Units V High Side Floating Supply Voltage -0.3 625 B V High Side Floating Supply Offset Voltage V - 25 V + 0.3 S B B V High Side Floating Output Voltage V - 0.3 V + 0.3 HO S B V Low Side Fixed Supply Voltage -0.3 25 CC V V Low Side Output Voltage -0.3 V + 0.3 LO CC V Logic Supply Voltage -0.3 V + 25 DD SS V Logic Supply Offset Voltage V - 25 V + 0.3 SS CC CC V Logic Input Voltage (HIN, LIN & SD) V - 0.3 V + 0.3 IN SS DD dV /dt Allowable Offset Supply Voltage Transient (Figure 2) 50 V/ns s P Package Power Dissipation T +25C (14 Lead DIP) 1.6 D A W (16 Lead SOIC) 1.25 R Thermal Resistance, Junction to Ambient (14 Lead DIP) 75 THJA C/W (16 Lead SOIC) 100 T Junction Temperature 150 J C T Storage Temperature -55 150 S T Lead Temperature (Soldering, 10 seconds) 300 L Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The V and V offset ratings are tested with all supplies biased at 15V differential. Typical S SS ratings at other bias conditions are shown in Figures 36 and 37. Symbol Definition Min. Max. Units V High Side Floating Supply Absolute Voltage V + 10 V + 20 B S S V High Side Floating Supply Offset Voltage Note 1 600 S V High Side Floating Output Voltage V V HO S B V Low Side Fixed Supply Voltage 10 20 CC V V Low Side Output Voltage 0 VCC LO V Logic Supply Voltage V + 3 V + 20 DD SS SS V Logic Supply Offset Voltage -5 (Note 2) 5 SS V Logic Input Voltage (HIN, LIN & SD) V V IN SS DD T Ambient Temperature -40 125 C A Note 1: Logic operational for V of -5 to +600V. Logic state held for V of -5V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). Note 2: When VDD < 5V, the minimum VSS offset is limited to -VDD. 2 www.irf.com