IR2113PBF Infineon

Data Sheet No. PD60147 rev. V IR2110(S)PbF/IR2113(S)PbF HIGH AND LOW SIDE DRIVER Features Product Summary Floating channel designed for bootstrap operation V (IR2110) 500V max. OFFSET Fully operational to +500V or +600V Tolerant to negative transient voltage (IR2113) 600V max. dV/dt immune Gate drive supply range from 10 to 20V I +/- 2A / 2A O Undervoltage lockout for both channels V 10 - 20V 3.3V logic compatible OUT Separate logic supply range from 3.3V to 20V t (typ.) 120 & 94 ns on/off Logic and power ground 5V offset CMOS Schmitt-triggered inputs with pull-down Delay Matching (IR2110) 10 ns max. Cycle by cycle edge-triggered shutdown logic (IR2113) 20ns max. Matched propagation delay for both channels Outputs in phase with inputs Packages Description The IR2110/IR2113 are high voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output chan- 16-Lead SOIC nels. Proprietary HVIC and latch immune CMOS technologies enable 14-Lead PDIP IR2110S/IR2113S ruggedized monolithic construction. Logic inputs are compatible with IR2110/IR2113 standard CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 500 or 600 volts. Typical Connection (Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.infineon.com/gatedriver 1IR2110(S)PbF/IR2113(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 28 through 35. Symbol Definition Min. Max. Units V High side floating supply voltage (IR2110) -0.3 525 B (IR2113) -0.3 625 V High side floating supply offset voltage V - 25 V + 0.3 S B B V High side floating output voltage V - 0.3 V + 0.3 HO S B V Low side fixed supply voltage -0.3 25 CC V V Low side output voltage -0.3 V + 0.3 LO CC V Logic supply voltage -0.3 V + 25 DD SS V Logic supply offset voltage V - 25 V + 0.3 SS CC CC V Logic input voltage (HIN, LIN & SD) V - 0.3 V + 0.3 IN SS DD dV /dt Allowable offset supply voltage transient (figure 2) 50 V/ns s P Package power dissipation T +25C (14 lead DIP) 1.6 D A W (16 lead SOIC) 1.25 R Thermal resistance, junction to ambient (14 lead DIP) 75 THJA C/W (16 lead SOIC) 100 T Junction temperature 150 J T Storage temperature -55 150 C S T Lead temperature (soldering, 10 seconds) 300 L Recommended Operating Conditions The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V and V offset ratings are tested with all supplies biased at 15V differential. Typical S SS ratings at other bias conditions are shown in figures 36 and 37. Symbol Definition Min. Max. Units V High side floating supply absolute voltage V + 10 V + 20 B S S V High side floating supply offset voltage (IR2110) Note 1 500 S (IR2113) Note 1 600 V High side floating output voltage V V HO S B V Low side fixed supply voltage 10 20 CC V V Low side output voltage 0 VCC LO V Logic supply voltage V + 3 V + 20 DD SS SS V Logic supply offset voltage -5 (Note 2) 5 SS V Logic input voltage (HIN, LIN & SD) V V IN SS DD T Ambient temperature -40 125 C A Note 1: Logic operational for V of -4 to +500V. Logic state held for V of -4V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). Note 2: When V < 5V, the minimum V offset is limited to -V DD SS DD. 2 www.infineon.com/gatedriver