IR2125SPBF Infineon

Data Sheet No. PD60017 Rev.Q ( ) & (PbF) IR2125 S CURRENT LIMITING SINGLE CHANNEL DRIVER Features Product Summary Floating channel designed for bootstrap operation V 500V max. OFFSET Fully operational to +500V Tolerant to negative transient voltage I +/- 1A / 2A dV/dt immune O Gate drive supply range from 12 to 18V Undervoltage lockout V 12 - 18V OUT Current detection and limiting loop to limit driven power transistor current V 230 mV CSth Error lead indicates fault conditions and programs shutdown time t (typ.) 150 & 150 ns on/off Output in phase with input 2.5V, 5V and 15V input logic compatible Packages Also available LEAD-Free Description The IR2125(S) is a high voltage, high speed power MOSFET and IGBT driver with over-current limiting protection circuitry. Proprietary HVIC and latch im- mune CMOS technologies enable ruggedized mono- lithic construction. Logic inputs are compatible with 16-Lead SOIC 8-Lead PDIP standard CMOS or LSTTL outputs, down to 2.5V (Wide Body) logic. The output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. The protection circuitry detects over-current in the driven power transistor and limits the gate drive voltage. Cycle by cycle shutdown is programmed by an external capacitor which directly controls the time interval between detection of the over-current limiting conditions and latched shutdown. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high or low side configuration which operates up to 500 volts. Typical Connection (Refer to Lead Assignments for correct pin configura- tion). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1( ) & (PbF) S IR2125 Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Max. Units V High Side Floating Supply Voltage -0.3 525 B V High Side Floating Offset Voltage V - 25 V + 0.3 S B B V High Side Floating Output Voltage V - 0.3 V + 0.3 HO S B V Logic Supply Voltage -0.3 25 V CC V Logic Input Voltage -0.3 V + 0.3 IN CC V Error Signal Voltage -0.3 V + 0.3 ERR CC V Current Sense Voltage V - 0.3 V + 0.3 CS S B dV /dt Allowable Offset Supply Voltage Transient 50 V/ns s P Package Power Dissipation T +25C (8 lead PDIP) 1.0 D A W (16 lead SOIC) 1.25 Rth Thermal Resistance, Junction to Ambient (8 lead PDIP) 125 JA C/W (16lLead SOIC) 100 T Junction Temperature 150 J T Storage Temperature -55 150 C S T Lead Temperature (Soldering, 10 seconds) 300 L Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The V offset rating is tested with all supplies biased at 15V differential. S Symbol Definition Min. Max. Units V High Side Floating Supply Voltage V + 12 V + 18 B S S V High Side Floating Offset Voltage Note 1 500 S V High Side Floating Output Voltage V V HO S B V Logic Supply Voltage 0 18 V CC V Logic Input Voltage 0 V IN CC V Error Signal Voltage 0 V ERR CC V Current Sense Signal Voltage V V CS S B T Ambient Temperature -40 125 C A Note 1: Logic operational for V of -5 to +500V. Logic state held for V of -5V to -V . (Please refer to the Design Tip S S BS DT97-3 for more details). 2 www.irf.com