Data Sheet No. PD60019 Rev.P IR2130/IR2132(J)(S) & (PbF) 3-PHASE BRIDGE DRIVER Product Summary Features Floating channel designed for bootstrap operation V 600V max. OFFSET Fully operational to +600V Tolerant to negative transient voltage I +/- 200 mA / 420 mA O dV/dt immune Gate drive supply range from 10 to 20V V 10 - 20V OUT Undervoltage lockout for all channels Over-current shutdown turns off all six drivers t (typ.) 675 & 425 ns on/off Independent half-bridge drivers Matched propagation delay for all channels Deadtime (typ.) 2.5 s (IR2130) 2.5V logic compatible Outputs out of phase with inputs 0.8 s (IR2132) Cross-conduction prevention logic Also available LEAD-FREE Packages Description The IR2130/IR2132(J)(S) is a high voltage, high speed power MOSFET and IGBT driver with three indepen- dent high and low side referenced output channels. Pro- prietary HVIC technology enables ruggedized 28-Lead SOIC monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 2.5V logic. A 28-Lead PDIP ground-referenced operational amplifier provides analog feedback of bridge current via an external cur- rent sense resistor. A current trip function which termi- 44-Lead PLCC w/o 12 Leads nates all six outputs is also derived from this resistor. An open drain FAULT signal indicates if an over-cur- rent or undervoltage shutdown has occurred. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use at high frequencies. The floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration which operate up to 600 volts. Typical Connection (Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1IR2130/IR2132(J)(S) & (PbF) Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to V . The Thermal Resistance and Power Dissipation ratings are measured S0 under board mounted and still air conditions. Additional information is shown in Figures 50 through 53. Symbol Definition Min. Max. Units V High Side Floating Supply Voltage -0.3 625 B1,2,3 V High Side Floating Offset Voltage V - 25 V + 0.3 S1,2,3 B1,2,3 B1,2,3 V High Side Floating Output Voltage V - 0.3 V + 0.3 HO1,2,3 S1,2,3 B1,2,3 V Low Side and Logic Fixed Supply Voltage -0.3 25 CC V Logic Ground V - 25 V + 0.3 SS CC CC V Low Side Output Voltage -0.3 V + 0.3 LO1,2,3 CC V HIN1,2,3 LIN1,2,3 V Logic Input Voltage ( , & ITRIP) V - 0.3 (V + 15) or IN SS SS (V + 0.3) CC whichever is lower V Output Voltage V - 0.3 V + 0.3 FAULT FLT SS CC V Operational Amplifier Output Voltage V - 0.3 V + 0.3 CAO SS CC V Operational Amplifier Inverting Input Voltage V - 0.3 V + 0.3 CA- SS CC dV /dt Allowable Offset Supply Voltage Transient 50 V/ns S P Package Power Dissipation TA +25C (28 Lead DIP) 1.5 D (28 Lead SOIC) 1.6 W (44 Lead PLCC) 2.0 Rth Thermal Resistance, Junction to Ambient (28 Lead DIP) 83 JA (28 Lead SOIC) 78 C/W (44 Lead PLCC) 63 T Junction Temperature 150 J T Storage Temperature -55 150 C S T Lead Temperature (Soldering, 10 seconds) 300 L Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to V . The V offset rating is tested S0 S with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in Figure 54. Symbol Definition Min. Max. Units V High Side Floating Supply Voltage V + 10 V + 20 B1,2,3 S1,2,3 S1,2,3 V High Side Floating Offset Voltage Note 1 600 S1,2,3 V High Side Floating Output Voltage V V HO1,2,3 S1,2,3 B1,2,3 V Low Side and Logic Fixed Supply Voltage 10 20 CC V Logic Ground -5 5 SS V Low Side Output Voltage 0 V LO1,2,3 CC V V Logic Input Voltage (HIN1,2,3, LIN1,2,3 & ITRIP) V V + 5 IN SS SS V FAULT Output Voltage V V FLT SS CC V Operational Amplifier Output Voltage V V + 5 CAO SS SS V Operational Amplifier Inverting Input Voltage V V + 5 CA- SS SS T Ambient Temperature -40 125 C A Note 1: Logic operational for V of (V - 5V) to (V + 600V). Logic state held for V of (V - 5V) to (V - V ). S S0 S0 S S0 S0 BS (Please refer to the Design Tip DT97-3 for more details). Note 2: All input pins, CA- and CAO pins are internally clamped with a 5.2V zener diode. 2 www.irf.com